summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz
2019-12-17ppc: Drop useless extern annotation for functionsGreg Kurz
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz
2019-12-17ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater
2019-12-17ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh
2019-12-17target/ppc: Add SPR ASDRSuraj Jitindar Singh
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater
2019-12-17ppc/psi: cleanup definitionsCédric Le Goater
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater
2019-12-17target/ppc: Add POWER10 DD1.0 model informationCédric Le Goater
2019-12-17ppc: Make PPCVirtualHypervisor an incomplete typeGreg Kurz
2019-12-17ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVMGreg Kurz
2019-12-17ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz
2019-12-17xics: Don't deassert outputsGreg Kurz
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz
2019-12-17spapr: Simplify ovec diffDavid Gibson
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson
2019-12-17spapr: Improve handling of fdt buffer sizeDavid Gibson
2019-12-17spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeoverDavid Gibson
2019-12-17ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy
2019-12-17ppc/pnv: Dump the XIVE NVT tableCédric Le Goater
2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater
2019-12-17ppc/xive: Synthesize interrupt from the saved IPB in the NVTCédric Le Goater
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater
2019-12-17spapr/xive: Configure number of servers in KVMGreg Kurz
2019-12-17spapr/xics: Configure number of servers in KVMGreg Kurz
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz
2019-12-17linux-headers: UpdateGreg Kurz
2019-12-17ppc/xive: Extend the TIMA operation with a XivePresenter parameterCédric Le Goater
2019-12-17ppc/xive: Use the XiveFabric and XivePresenter interfacesCédric Le Goater
2019-12-17ppc/spapr: Implement the XiveFabric interfaceCédric Le Goater
2019-12-17ppc/pnv: Implement the XiveFabric interfaceCédric Le Goater
2019-12-17ppc/xive: Introduce a XiveFabric interfaceCédric Le Goater
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater
2019-12-17ppc/pnv: Loop on the threads of the chip to find a matching NVTCédric Le Goater
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 01:55:44 +0000