summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-09-25Merge remote-tracking branch 'bonzini/scsi-next' into stagingAnthony Liguori
* bonzini/scsi-next: SCSI: Standard INQUIRY data should report HiSup flag as set. scsi-disk: use scsi_data_cdb_length scsi: introduce scsi_cdb_length and scsi_data_cdb_length scsi-disk: fix check for out-of-range LBA scsi-disk: introduce check_lba_range iSCSI: We dont need to explicitely call qemu_notify_event() any more iSCSI: We need to support SG_IO also from iscsi_ioctl()
2012-09-25Merge remote-tracking branch 'bonzini/nbd-next' into stagingAnthony Liguori
* bonzini/nbd-next: nbd: add nbd_export_get_blockdev nbd: negotiate with named exports nbd: register named exports qemu-nbd: rewrite termination conditions to use a state machine nbd: add notification for closing an NBDExport nbd: track clients into NBDExport nbd: add reference counting to NBDExport nbd: do not leak nbd_trip coroutines when a connection is torn down nbd: make refcount interface public nbd: do not close BlockDriverState in nbd_export_close nbd: pass NBDClient to nbd_send_negotiate nbd: add more constants
2012-09-23w32: Add implementation of gmtime_r, localtime_rStefan Weil
Those functions are missing in MinGW. Some versions of MinGW-w64 include defines for gmtime_r and localtime_r. Older versions of these macros are buggy (they return a pointer to a static variable), therefore we don't want them. Newer versions are similar to the code used here, but without the memset. The implementation which is used here is not strictly reentrant, but sufficiently good for QEMU on w32 or w64. Signed-off-by: Stefan Weil <sw@weilnetz.de> [blauwirbel@gmail.com: added comment about locking] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-23audio: Fix warning from static code analysisStefan Weil
smatch report: audio/audio_template.h:416 AUD_open_out(18) warn: variable dereferenced before check 'as' (see line 414) Moving the ldebug statement after the statement which checks 'as' fixes that warning. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: malc <av1474@comtv.ru>
2012-09-22Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rthBlue Swirl
* 'tcg-sparc' of git://repo.or.cz/qemu/rth: tcg-sparc: Preserve branch destinations during retranslation tcg-sparc: Fix and enable direct TB chaining. tcg-sparc: Add %g/%o registers to alloc_order tcg-sparc: Use defines for temporaries. tcg-sparc: Mask shift immediates to avoid illegal insns. tcg-sparc: Clean up cruft stemming from attempts to use global registers. tcg-sparc: Change AREG0 in generated code to %i0. tcg-sparc: Support GUEST_BASE. tcg-sparc: Fix qemu_ld/st to handle 32-bit host. tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. tcg-sparc: Don't MAP_FIXED on top of the program tcg-sparc: Fix ADDX opcode. tcg-sparc: Hack in qemu_ld/st64 for 32-bit. linux-user: Use memcpy in get_user/put_user.
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov
In case Coprocessor Context option is enabled CPENABLE SR bits control whether access to coprocessors is allowed or would rise one of CoprocessorXDisabled exceptions. See ISA, 4.4.5 for more details. FP is coprocessor 0. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement FP1 groupMax Filippov
These are comparison and conditional move opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov
These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that ISA description for utrunc.s is currently incorrect and will be fixed in future revisions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov
These are FP arithmetic opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov
These are load/store instructions for FP registers with immediate or register index and optional base post-update. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: add FP registersMax Filippov
There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: specialize softfloat NaN rulesMax Filippov
NaN propagation rule: leftmost NaN in the expression gets propagated to the result. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: handle boolean option in overlaysMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22softfloat: add NO_SIGNALING_NANSMax Filippov
Architectures that don't have signaling NaNs can define NO_SIGNALING_NANS, it will make float*_is_quiet_nan return 1 for any NaN and float*_is_signaling_nan always return 0. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22softfloat: make float_muladd_negate_* flags independentMax Filippov
Flags passed into float{32,64}_muladd are treated as bits; assign independent bits to float_muladd_negate_* to allow precise control over what gets negated in float{32,64}_muladd. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22Revert "tcg/mips"Aurelien Jarno
This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad. This commit was not supposed to be pushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/ppc32: Implement movcond32malc
Thanks to Richard Henderson Signed-off-by: malc <av1474@comtv.ru>
2012-09-22tcg/mipsAurelien Jarno
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/i386: Remove unused registers from tcg_target_call_iarg_regsStefan Weil
32 bit x86 hosts don't need registers for helper function arguments because they use the default stack based calling convention. Removing the registers allows simpler code for function tcg_target_get_call_iarg_regs_count. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/i386: Add shortcuts for registers used in L constraintStefan Weil
While 64 bit hosts use the first three registers which are also used as function input parameters, 32 bit hosts use TCG_REG_EAX and TCG_REG_EDX which are not used in parameter passing. After defining new register macros for the registers used in L constraint, the patch replaces most occurrences of tcg_target_call_iarg_regs[0], tcg_target_call_iarg_regs[1] and tcg_target_call_iarg_regs[2] by those new macros. tcg_target_call_iarg_regs remains unchanged when it is used for input arguments (only with 64 bit hosts) before tcg_out_calli. A comment related to those registers was fixed, too. Signed-off-by: Stefan Weil <sw@weilnetz.de> [aurel32: build fix on i386, small optimization for i386 in the prologue] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22w64: Fix TCG helper functions with 5 argumentsStefan Weil
TCG uses 6 registers for function arguments on 64 bit Linux hosts, but only 4 registers on W64 hosts. Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number of arguments for some important helper functions from 4 to 5 which triggered a bug for W64 hosts: QEMU aborts when executing helper_lcall_real in the guest's BIOS because function tcg_target_get_call_iarg_regs_count always returned 6. As W64 has only 4 registers for arguments, the 5th argument must be passed on the stack using a correct stack offset. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/README: document tcg_gen_goto_tb restrictionsMax Filippov
See http://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.html for the whole story. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg-hppa: Implement movcondRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: add constant folding for depositAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg: remove #ifdef #endif around TCGOpcode testsAurelien Jarno
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't need to #ifdef #endif the one that are available only on some targets. This makes the code easier to read. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: prefer the "op a, a, b" form for commutative opsAurelien Jarno
The "op a, a, b" form is better handled on non-RISC host than the "op a, b, a" form, so swap the arguments to this form when possible, and when b is not a constant. This reduces the number of generated instructions by a tiny bit. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: further optimize brcond/movcond/setcondAurelien Jarno
When both argument of brcond/movcond/setcond are the same or when one of the two values is a constant equal to zero, it's possible to do further optimizations. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: optimize "op r, a, a => movi r, 0"Aurelien Jarno
Now that it's possible to detect copies, we can optimize the case the "op r, a, a => movi r, 0". This helps in the computation of overflow flags when one of the two args is 0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: optimize "op r, a, a => mov r, a"Aurelien Jarno
Now that we can easily detect all copies, we can optimize the "op r, a, a => mov r, a" case a bit more. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: do copy propagation for all operationsAurelien Jarno
It is possible to due copy propagation for all operations, even the one that have side effects or clobber arguments (it only concerns input arguments). That said, the call operation should be handled differently due to the variable number of arguments. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: rework copy progagationAurelien Jarno
The copy propagation pass tries to keep track what is a copy of what and what has copy of what, and in addition it keep a circular list of of all the copies. Unfortunately this doesn't fully work: a mov from a temp which has a state "COPY" changed it into a state "HAS_COPY". Later when this temp is used again, it is considered has not having copy and thus no propagation is done. This patch fixes that by removing the hiearchy between copies, and thus only keeping a "COPY" state both meaning "is a copy" and "has a copy". The decision of which copy to use is deferred to the actual temp replacement. At this stage there is not one best choice to do, but only better choices than others. For doing the best choice the operation would have to be parsed in reversed to know if a temp is going to be used later or not. That what is done by the liveness analysis. At this stage it is known that globals will be always live, that local temps will be dead at the end of the translation block, and that the temps will be dead at the end of the basic block. This means that this stage should try to replace temps by local temps or globals and local temps by globals. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: check types in copy propagationAurelien Jarno
The copy propagation doesn't check the types of the temps during copy propagation. However TCG is using the mov_i32 for the i64 to i32 conversion and thus the two are not equivalent. With this patch tcg_opt_gen_mov() doesn't consider two temps of different type as copies anymore. So far it seems the optimization was not aggressive enough to trigger this bug, but it will be triggered later in this series once the copy propagation is improved. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: remove TCG_TEMP_ANYAurelien Jarno
TCG_TEMP_ANY has no different meaning than TCG_TEMP_UNDEF, so use the later instead. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement movcond op on MIPS32R2Aurelien Jarno
movcond operation can be implemented on MIPS32 Release 2 using the MOVN, MOVZ, SLT and SLTU instructions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement deposit op on MIPS32R2Aurelien Jarno
deposit operations can be optimized on MIPS32 Release 2 using the INS instruction. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement rotl/rotr ops on MIPS32R2Aurelien Jarno
rotr operations can be optimized on MIPS32 Release 2 using the ROTR and ROTRV instructions. Also implemented rotl operations by subtracting the shift from 32. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: optimize bswap{16,16s,32} on MIPS32R2Aurelien Jarno
bswap operations can be optimized on MIPS32 Release 2 using the ROTR, WSBH and SEH instructions. We can't use the non-R2 code to implement the ops due to registers constraints, so don't define the corresponding TCG_TARGET_HAS_bswap* values. Also bswap16* operations are supposed to be called with the 16 high bits zeroed. This is the case everywhere (including for TCG by definition) except when called from the store helper. Remove the AND instructions from bswap16* and move it there. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: optimize brcond arg, 0Aurelien Jarno
MIPS has some conditional branch instructions when comparing with zero. Use them. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: use stack for TCG tempsAurelien Jarno
Use stack instead of temp_buf array in CPUState for TCG temps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: don't use global pointerAurelien Jarno
Don't use the global pointer in TCG, in case helpers try access global variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: use TCGArg or TCGReg instead of intAurelien Jarno
Instead of int, use the correct TCGArg and TCGReg type: TCGReg when representing a TCG target register, TCGArg when representing the latter or a constant. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: kill warnings in user modeAurelien Jarno
Recent versions of GCC emit warnings when compiling user mode targets. Kill them by reordering a bit the #ifdef. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg-mips: fix wrong usage of 'Z' constraintAurelien Jarno
The 'Z' constraint has been introduced to map the zero register. However when the op also accept a constant, there is no point to accept the zero register in addition. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg-sparc: Preserve branch destinations during retranslationRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix and enable direct TB chaining.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Add %g/%o registers to alloc_orderRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Use defines for temporaries.Richard Henderson
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Mask shift immediates to avoid illegal insns.Richard Henderson
The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Clean up cruft stemming from attempts to use global registers.Richard Henderson
Don't use -ffixed-gN. Don't link statically. Don't save/restore AREG0 around calls. Don't allocate space on the stack for AREG0 save. Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:04:15 +0000