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2019-05-15vl: Add missing descriptions to the VGA adapters listPhilippe Mathieu-Daudé
Some VGA adapters do not contain an helpful description, this can be confusing: $ qemu-system-arm -M virt -vga help none std standard VGA cirrus Cirrus VGA (default) vmware VMWare SVGA xenfb Add a description to the missing adapters: $ qemu-system-arm -M virt -vga help none no graphic card std standard VGA cirrus Cirrus VGA (default) vmware VMWare SVGA xenfb Xen paravirtualized framebuffer Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Based-on: <20190412152713.16018-1-marcandre.lureau@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Message-Id: <20190412163706.3878-1-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15Declare -realtime as deprecatedThomas Huth
The old -realtime mlock=on|off parameter does exactly the same as the new -overcommit mem-lock=on|off parameter. Additionally, "-realtime" does not activate any additional "realtime" capabilities as the name might indicate. We should avoid to confuse the users this way, so let's deprecate the old -realtime option. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190411175345.19414-1-thuth@redhat.com>
2019-05-15roms: assert if max rom size is less than the used sizeIgor Mammedov
It would ensure that we would notice attempt to write beyond the allocated buffer. In case of MemoryRegion backed ROM it's the host buffer and the guest RAM otherwise. assert can be triggered with: dd if=/dev/zero of=/tmp/blob bs=63k count=1 qemu-system-x86_64 `for i in {1..33}; do echo -n " -acpitable /tmp/blob"; done` Fixes: (a1666142db acpi-build: make ROMs RAM blocks resizeable) Reported-by: Wei Yang <richardw.yang@linux.intel.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1554982098-336210-1-git-send-email-imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15hw/input: Add a CONFIG_PS2 switch for the ps2.c fileThomas Huth
ps2.c only needs to be compiled if we are building pckbd.c or pl050.c. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190411182240.5957-1-thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-14Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190513' into stagingPeter Maydell
Improve code generation for vector duplication. Add vector expansions for shifts by non-constant scalar. Add vector expansions for shifts by vector. Add integer and vector expansions for absolute value. Several patches in preparation for Altivec. Bug fix for tcg/aarch64 vs min/max. # gpg: Signature made Tue 14 May 2019 00:58:02 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190513: (31 commits) tcg/aarch64: Do not advertise minmax for MO_64 target/xtensa: Use tcg_gen_abs_i32 target/tricore: Use tcg_gen_abs_tl target/s390x: Use tcg_gen_abs_i64 target/ppc: Use tcg_gen_abs_tl target/ppc: Use tcg_gen_abs_i32 target/cris: Use tcg_gen_abs_tl target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs tcg/aarch64: Support vector absolute value tcg/i386: Support vector absolute value tcg: Add support for vector absolute value tcg: Add support for integer absolute value tcg/i386: Support vector scalar shift opcodes tcg: Add gvec expanders for vector shift by scalar tcg/aarch64: Support vector variable shift opcodes tcg/i386: Support vector variable shift opcodes tcg: Add gvec expanders for variable shift tcg: Add INDEX_op_dupm_vec tcg/aarch64: Implement tcg_out_dupm_vec tcg/i386: Implement tcg_out_dupm_vec ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13tcg/aarch64: Do not advertise minmax for MO_64Richard Henderson
The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/xtensa: Use tcg_gen_abs_i32Richard Henderson
Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/tricore: Use tcg_gen_abs_tlPhilippe Mathieu-Daudé
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/s390x: Use tcg_gen_abs_i64Richard Henderson
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_tlRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_i32Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/cris: Use tcg_gen_abs_tlRichard Henderson
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_absRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/aarch64: Support vector absolute valueRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector absolute valueRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add support for vector absolute valueRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add support for integer absolute valueRichard Henderson
Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector scalar shift opcodesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add gvec expanders for vector shift by scalarRichard Henderson
Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Use a private structure for do_gvec_shifts.
2019-05-13tcg/aarch64: Support vector variable shift opcodesRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector variable shift opcodesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add gvec expanders for variable shiftRichard Henderson
The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add INDEX_op_dupm_vecRichard Henderson
Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Note that officially tcg_out_dupm_vec is allowed to fail. If it did, we could fix this up relatively easily: VECE == 32/64: Load the value into a vector register, then dup. Both of these must work. VECE == 8/16: If the value happens to be at an offset such that an aligned load would place the desired value in the least significant end of the register, go ahead and load w/garbage in high bits. Load the value w/INDEX_op_ld{8,16}_i32. Attempt a move directly to vector reg, which may fail. Store the value into the backing store for OTS. Load the value into the vector reg w/TCG_TYPE_I32, which must work. Duplicate from the vector reg into itself, which must work. All of which is well and good, except that all supported hosts can support dupm for all vece, so all of the failure paths would be dead code and untestable. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/aarch64: Implement tcg_out_dupm_vecRichard Henderson
The LD1R instruction does all the work. Note that the only useful addressing mode is a base register with no offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Implement tcg_out_dupm_vecRichard Henderson
At the same time, improve tcg_out_dupi_vec wrt broadcast from the constant pool. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add tcg_out_dupm_vec to the backend interfaceRichard Henderson
Currently stubbed out in all backends that support vectors. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Manually expand INDEX_op_dup_vecRichard Henderson
This case is similar to INDEX_op_mov_* in that we need to do different things depending on the current location of the source. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Added some commentary to the tcg_reg_alloc_* functions.
2019-05-13tcg: Promote tcg_out_{dup,dupi}_vec to backend interfaceRichard Henderson
The i386 backend already has these functions, and the aarch64 backend could easily split out one. Nothing is done with these functions yet, but this will aid register allocation of INDEX_op_dup_vec in a later patch. Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Support cross-class moves without instruction supportRichard Henderson
PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson
This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/arm: Use tcg_out_mov_reg in tcg_out_movRichard Henderson
We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Assert fixed_reg is read-onlyRichard Henderson
The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Specify optional vector requirements with a listRichard Henderson
Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expandedRichard Henderson
PowerPC Altivec does not support add and subtract of 64-bit elements. Prepare for that configuration by not assuming the operation is universally supported. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Do not recreate INDEX_op_neg_vec unless supportedRichard Henderson
Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec, so that we check the type and vece for the actual operation. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Implement tcg_gen_gvec_3i()David Hildenbrand
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed for now. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190416185301.25344-2-david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13Merge remote-tracking branch ↵Peter Maydell
'remotes/huth-gitlab/tags/pull-request-2019-05-13' into staging Kconfig settings for the Arm machines # gpg: Signature made Mon 13 May 2019 09:19:43 BST # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2019-05-13: (29 commits) hw/arm: Remove hard-enablement of the remaining PCI devices hw/arm: Express dependencies of the musca machines with Kconfig hw/arm: Express dependencies of the xlnx-versal-virt machine with Kconfig hw/arm: Express dependencies of the ZynqMP zcu102 machine with Kconfig hw/arm: Express dependencies of the microbit / nrf51 machine with Kconfig hw/arm: Express dependencies of the remaining IMX boards with Kconfig hw/arm: Express dependencies of the MSF2 / EMCRAFT_SF2 machine with Kconfig hw/arm: Express dependencies of sabrelite with Kconfig hw/arm: Express dependencies of canon-a1100 with Kconfig hw/arm: Express dependencies of the raspi machines with Kconfig hw/arm: Express dependencies of the MPS2 boards with Kconfig hw/arm: Express dependencies of allwinner / cubieboard with Kconfig hw/arm: Express dependencies of netduino / stm32f2xx with Kconfig hw/arm: Express dependencies of the virt machine with Kconfig hw/arm: Express dependencies of the aspeed boards with Kconfig hw/arm: Express dependencies of collie with Kconfig hw/arm: Express dependencies of xilinx-zynq with Kconfig hw/arm: Express dependencies of the PXA2xx machines with Kconfig hw/arm: Express dependencies of realview, versatile and vexpress with Kconfig hw/arm: Express dependencies of stellaris with Kconfig ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2019-05-13' into ↵Peter Maydell
staging Miscellaneous patches for 2019-05-13 # gpg: Signature made Mon 13 May 2019 08:04:02 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2019-05-13: Clean up decorations and whitespace around header guards Normalize header guard symbol definition. Clean up ill-advised or unusual header guards Clean up header guards that don't match their file name target/xtensa: Clean up core-isa.h header guards linux-user/nios2 linux-user/riscv: Clean up header guards authz: Normalize #include "authz/trace.h" to "trace.h" Use #include "..." for our own headers, <...> for others Clean up includes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/input-20190513-v2-pull-request' into staging input: add vhost-user-input, virtio-input fixes. # gpg: Signature made Mon 13 May 2019 07:52:39 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/input-20190513-v2-pull-request: virtio-input: fix Kconfig dependency and Makefile virtio-input-host-pci: cleanup types util: simplify unix_listen() Add vhost-user-input-pci Add vhost-user-backend libvhost-user: add PROTOCOL_F_CONFIG if {set, get}_config libvhost-user: fix -Waddress-of-packed-member Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-demacro-softmmu-100519-1' into staging Demacrofy the SoftMMU - the demacro itself - refactor TLB_RECHECK and fix bug - move unaligned handler out # gpg: Signature made Fri 10 May 2019 20:34:14 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-demacro-softmmu-100519-1: cputlb: Do unaligned store recursion to outermost function cputlb: Do unaligned load recursion to outermost function cputlb: Drop attribute flatten cputlb: Move TLB_RECHECK handling into load/store_helper accel/tcg: demacro cputlb Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13hw/arm: Remove hard-enablement of the remaining PCI devicesThomas Huth
The PCI devices should be pulled in by default if PCI_DEVICES is set, so there is no need anymore to enforce them in the configs file. Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the musca machines with KconfigThomas Huth
Dependencies have been determined with trial-and-error and by looking at the musca.c source file. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the xlnx-versal-virt machine with KconfigThomas Huth
Dependencies have been determined with trial-and-error and by looking at the xlnx-versal.c source file. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the ZynqMP zcu102 machine with KconfigThomas Huth
This cleans up most settings in default-configs/aarch64-softmmu.mak. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the microbit / nrf51 machine with KconfigThomas Huth
Add Kconfig dependencies for the NRF51 / microbit machine. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the remaining IMX boards with KconfigThomas Huth
IMX25, IMX7 and IMX6UL were still missing the Kconfig dependencies. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the MSF2 / EMCRAFT_SF2 machine with KconfigThomas Huth
Add Kconfig dependencies for the emcraft-sf2 machine - we also distinguish between the machine (CONFIG_EMCRAFT_SF2) and the SoC (CONFIG_MSF2) now. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of sabrelite with KconfigThomas Huth
Add Kconfig dependencies for the Sabrelite / iMX6 machine. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of canon-a1100 with KconfigThomas Huth
Add Kconfig dependencies for the DIGIC / canon-a1100 machine. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-05-13hw/arm: Express dependencies of the raspi machines with KconfigThomas Huth
Most of the code is directly controlled by the CONFIG_RASPI switch, so not much to add here additionally. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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