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2021-02-25Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-updates-240221-1' into staging Testing tweaks (build, docs, bumps) - expose cross compiler info in meson pretty print - bump Fedora to 33 - "graceful" handling of missing virgl config - updates to the container documentation - move CODING_STYLE.rst into developer manual # gpg: Signature made Wed 24 Feb 2021 11:08:03 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-updates-240221-1: docs: move CODING_STYLE into the developer documentation docs/devel: add forward reference to check-tcg docs/devel: update the container based tests docs/devel: expand on use of containers to build tests tests/acceptance: allow a "graceful" failing for virtio-gpu test docker: Bump Fedora images to release 33 meson.build: expose TCG cross compiler information in summary Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-25Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pc,virtio,pci: fixes, tests Fixes all over the place, a new test. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 23 Feb 2021 16:00:29 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: qtest/acpi/bios-tables-test: update acpi tables acpi: add test case for -no-hpet i386: acpi: Don't build HPET ACPI entry if HPET is disabled hw/i386: declare ACPI mother board resource for MMCONFIG region acpi: add test case for smm unsupported -machine smm=off acpi: set fadt.smi_cmd to zero when SMM is not supported acpi/core: always set SCI_EN when SMM isn't supported ich9, piix4: add property, smm-compat, to keep compatibility of SMM qtest: update tests/qtest/bios-tables-test-allowed-diff.h checkpatch: don't emit warning on newly created acpi data files tests/data/acpi/virt/DSDT.pxb: update with _CCA acpi/gpex: Fix cca attribute check for pxb device acpi: Allow pxb DSDT acpi table changes pcie: don't set link state active if the slot is empty failover: really display a warning when the primary device is not found virtio-net: add missing object_unref() pci: cleanup failover sanity check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-24docs: move CODING_STYLE into the developer documentationAlex Bennée
There is no particular reason to keep this on it's own in the root of the tree. Move it into the rest of the fine developer manual and fixup any links to it. The only tweak I've made is to fix the code-block annotations to mention the language C. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210223095931.16908-1-alex.bennee@linaro.org>
2021-02-24docs/devel: add forward reference to check-tcgAlex Bennée
For completeness reference the check-tcg tests in the container preamble text. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20210222101455.12640-7-alex.bennee@linaro.org>
2021-02-24docs/devel: update the container based testsAlex Bennée
This section has grown a little stale so clean-up the language and examples for current usage: - refer to containers at the top - mention podman can also be used - add podman prerequisites section - move to using "docker-help" for online help - mention the registry and it's purpose - don't refer to out-of-date min-glib image Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210222101455.12640-6-alex.bennee@linaro.org>
2021-02-24docs/devel: expand on use of containers to build testsAlex Bennée
Expand on the usage of containers for building tests and why we have some that are not used to build QEMU itself. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20210222101455.12640-5-alex.bennee@linaro.org>
2021-02-24tests/acceptance: allow a "graceful" failing for virtio-gpu testAlex Bennée
This is a band-aid with a TODO for cases when QEMU doesn't start due to missing VirGL. Longer term we could do with some proper feature probing. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210222101455.12640-4-alex.bennee@linaro.org>
2021-02-24docker: Bump Fedora images to release 33Philippe Mathieu-Daudé
Fedora 33 was released on October 27, 2020. Update all the Fedora 32 images to this new release. Suggested-by: Daniel Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210118181255.314672-1-philmd@redhat.com> Message-Id: <20210222101455.12640-3-alex.bennee@linaro.org>
2021-02-24meson.build: expose TCG cross compiler information in summaryAlex Bennée
Blink and you miss the cross TCG compiler stuff so lets display it with the rest of the compiler information. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222101455.12640-2-alex.bennee@linaro.org>
2021-02-23qtest/acpi/bios-tables-test: update acpi tablesIsaku Yamahata
update golden master acpi tables and empty bios-tables-test-allowed-diff.h. Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <de5a7f88563d39ed0cec34ff1d4cd6a1bdc927f0.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23acpi: add test case for -no-hpetIsaku Yamahata
Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <5ef9a81e49793afb42ffd19bbf1f44e269c65e93.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23i386: acpi: Don't build HPET ACPI entry if HPET is disabledSean Christopherson
Omit HPET AML if the HPET is disabled, QEMU is not emulating it and the guest may get confused by seeing HPET in the ACPI tables without a "physical" device present. The change of DSDT when -no-hpet is as follows. @@ -141,47 +141,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " } } - Scope (_SB) - { - Device (HPET) - { - Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID - OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) - Field (HPTM, DWordAcc, Lock, Preserve) - { - VEND, 32, - PRD, 32 - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Local0 = VEND /* \_SB_.HPET.VEND */ - Local1 = PRD /* \_SB_.HPET.PRD_ */ - Local0 >>= 0x10 - If (((Local0 == Zero) || (Local0 == 0xFFFF))) - { - Return (Zero) - } - - If (((Local1 == Zero) || (Local1 > 0x05F5E100))) - { - Return (Zero) - } - - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadOnly, - 0xFED00000, // Address Base - 0x00000400, // Address Length - ) - }) - } - } - Scope (_SB.PCI0) { Device (ISA) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Message-Id: <66114dead09232d04891b9e5f5a4081e85cc2c4d.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23hw/i386: declare ACPI mother board resource for MMCONFIG regionIsaku Yamahata
Declare PNP0C01 device to reserve MMCONFIG region to conform to the spec better and play nice with guest BIOSes/OSes. According to PCI Firmware Specification[0], MMCONFIG region must be reserved by declaring a motherboard resource. It's optional to reserve the region in memory map by Int 15 E820h or EFIGetMemoryMap. Guest Linux checks if the MMCFG region is reserved by bios memory map or ACPI resource. If it's not reserved, Linux falls back to legacy PCI configuration access. TDVF [1] [2] doesn't reserve MMCONFIG the region in memory map. On the other hand OVMF reserves it in memory map without declaring a motherboard resource. With memory map reservation, linux guest uses MMCONFIG region. However it doesn't comply to PCI Firmware specification. [0] PCI Firmware specification Revision 3.2 4.1.2 MCFG Table Description table 4-2 NOTE 2 If the operating system does not natively comprehend reserving the MMCFG region, The MMCFG region must e reserved by firmware. ... For most systems, the mortheroard resource would appear at the root of the ACPI namespace (under \_SB)... The resource can optionally be returned in Int15 E820h or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource [1] TDX: Intel Trust Domain Extension https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html [2] TDX Virtual Firmware https://github.com/tianocore/edk2-staging/tree/TDVF The change to DSDT is as follows. @@ -68,32 +68,47 @@ If ((CDW3 != Local0)) { CDW1 |= 0x10 } CDW3 = Local0 } Else { CDW1 |= 0x04 } Return (Arg3) } } + + Device (DRAC) + { + Name (_HID, "PNP0C01" /* System Board */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xB0000000, // Range Minimum + 0xBFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x10000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } } Scope (_SB) { Device (HPET) { Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) Field (HPTM, DWordAcc, Lock, Preserve) { VEND, 32, PRD, 32 } Method (_STA, 0, NotSerialized) // _STA: Status Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <6f686b45ce7bc43048c56dbb46e72e1fe51927e6.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2021-02-23acpi: add test case for smm unsupported -machine smm=offIsaku Yamahata
Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <22f774a51255af1608b07b00b257af426adcf4ab.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23acpi: set fadt.smi_cmd to zero when SMM is not supportedIsaku Yamahata
>From table 5.9 SMI_CMD of ACPI spec > This field is reserved and must be zero on system > that does not support System Management mode. When smm is not enabled, set it to zero to comform to the spec. When -machine smm=off is passed, the change to FACP is as follows. @@ -1,46 +1,46 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180105 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Fri Feb 5 16:57:04 2021 + * Disassembly of /tmp/aml-1OQYX0, Fri Feb 5 16:57:04 2021 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : D6 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPCFACP" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] FACS Address : 00000000 [028h 0040 4] DSDT Address : 00000000 [02Ch 0044 1] Model : 01 [02Dh 0045 1] PM Profile : 00 [Unspecified] [02Eh 0046 2] SCI Interrupt : 0009 -[030h 0048 4] SMI Command Port : 000000B2 -[034h 0052 1] ACPI Enable Value : 02 -[035h 0053 1] ACPI Disable Value : 03 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 [038h 0056 4] PM1A Event Block Address : 00000600 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00000604 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00000000 [04Ch 0076 4] PM Timer Block Address : 00000608 [050h 0080 4] GPE0 Block Address : 00000620 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 00 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 10 [05Dh 0093 1] GPE1 Block Length : 00 Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <09ed791ef77fda2b194100669cbc690865c9eb52.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23acpi/core: always set SCI_EN when SMM isn't supportedIsaku Yamahata
If SMM is not supported, ACPI fixed hardware doesn't support legacy-mode. ACPI-only platform. Where SCI_EN in PM1_CNT register is always set. The bit tells OS legacy mode(SCI_EN cleared) or ACPI mode(SCI_EN set). With the next patch (setting fadt.smi_cmd = 0 when smm isn't enabled), guest Linux tries to switch to ACPI mode, finds smi_cmd = 0, and then fails to initialize acpi subsystem. This patch proactively fixes it. This patch changes guest ABI. To keep compatibility, use "smm-compat" introduced by earlier patch. If the property is true, disable new behavior. ACPI spec 4.8.10.1 PM1 Event Grouping PM1 Eanble Registers > For ACPI-only platforms (where SCI_EN is always set) Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <500f62081626997e46f96377393d3662211763a8.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23ich9, piix4: add property, smm-compat, to keep compatibility of SMMIsaku Yamahata
The following patch will introduce incompatible behavior of SMM. Introduce a property to keep the old behavior for compatibility. To enable smm compat, use "-global ICH9-LPC.smm-compat=on" or "-global PIIX4_PM.smm-compat=on" Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <47254ae0b8c6cc6945422978b6b2af2d213ef891.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2021-02-23qtest: update tests/qtest/bios-tables-test-allowed-diff.hIsaku Yamahata
The following tests will modify acpi tables. prepare qtests to allow acpi table change. add new tables for new tests. - tests/data/acpi/pc/DSDT.nohpet - tests/data/acpi/pc/FACP.nosmm - tests/data/acpi/q35/DSDT.nohpet - tests/data/acpi/q35/FACP.nosmm Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <c8285f54deab362ed839d31f0fb5bb590ab71fdd.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23checkpatch: don't emit warning on newly created acpi data filesIsaku Yamahata
Newly created acpi data files(tests/data/acpi/) cause false positive warning. If file names are acpi expected file, don't emit warning. Fixes: e625ba2a41 ("checkpatch: fix acpi check with multiple file name") Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Message-Id: <6899f9ad54cab8e7deca94ff0eeab641680e2b5e.1613615732.git.isaku.yamahata@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23tests/data/acpi/virt/DSDT.pxb: update with _CCAXingang Wang
Update expected DSDT files accordingly, and re-enable their testing. diff of disassembly of changed expected files: diff -ru -IDisassembly old/tests/data/acpi/virt/DSDT.pxb.dsl new/tests/data/acpi/virt/DSDT.pxb.dsl --- old/tests/data/acpi/virt/DSDT.pxb.dsl 2021-02-23 09:54:18.566781350 -0500 +++ new/tests/data/acpi/virt/DSDT.pxb.dsl 2021-02-23 09:57:51.952816428 -0500 Name (_BBN, 0x80) // _BBN: BIOS Bus Number Name (_UID, 0x80) // _UID: Unique ID Name (_STR, Unicode ("pxb Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23acpi/gpex: Fix cca attribute check for pxb deviceXingang Wang
When check DMA support for device attached to pxb, the cache coherency attribute need to be set. This add _CCA attribute for pxb DSDT. Fixes: 6f9765fbad ("acpi/gpex: Build tables for pxb") Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1612490205-48788-3-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2021-02-23acpi: Allow pxb DSDT acpi table changesXingang Wang
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1612490205-48788-2-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2021-02-23pcie: don't set link state active if the slot is emptyLaurent Vivier
When the pcie slot is initialized, by default PCI_EXP_LNKSTA_DLLLA (Data Link Layer Link Active) is set in PCI_EXP_LNKSTA (Link Status) without checking if the slot is empty or not. This is confusing for the kernel because as it sees the link is up it tries to read the vendor ID and fails: (From https://bugzilla.kernel.org/show_bug.cgi?id=211691) [ 1.661105] pcieport 0000:00:02.2: pciehp: Slot Capabilities : 0x0002007b [ 1.661115] pcieport 0000:00:02.2: pciehp: Slot Status : 0x0010 [ 1.661123] pcieport 0000:00:02.2: pciehp: Slot Control : 0x07c0 [ 1.661138] pcieport 0000:00:02.2: pciehp: Slot #0 AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise+ Interlock+ NoCompl- IbPresDis- LLActRep+ [ 1.662581] pcieport 0000:00:02.2: pciehp: pciehp_get_power_status: SLOTCTRL 6c value read 7c0 [ 1.662597] pcieport 0000:00:02.2: pciehp: pciehp_check_link_active: lnk_status = 2204 [ 1.662703] pcieport 0000:00:02.2: pciehp: pending interrupts 0x0010 from Slot Status [ 1.662706] pcieport 0000:00:02.2: pciehp: pcie_enable_notification: SLOTCTRL 6c write cmd 1031 [ 1.662730] pcieport 0000:00:02.2: pciehp: pciehp_check_link_active: lnk_status = 2204 [ 1.662748] pcieport 0000:00:02.2: pciehp: pciehp_check_link_active: lnk_status = 2204 [ 1.662750] pcieport 0000:00:02.2: pciehp: Slot(0-2): Link Up [ 2.896132] pcieport 0000:00:02.2: pciehp: pciehp_check_link_status: lnk_status = 2204 [ 2.896135] pcieport 0000:00:02.2: pciehp: Slot(0-2): No device found [ 2.896900] pcieport 0000:00:02.2: pciehp: pending interrupts 0x0010 from Slot Status [ 2.896903] pcieport 0000:00:02.2: pciehp: pciehp_power_off_slot: SLOTCTRL 6c write cmd 400 [ 3.656901] pcieport 0000:00:02.2: pciehp: pending interrupts 0x0009 from Slot Status This is really a problem with virtio-net failover that hotplugs a VFIO card during the boot process. The kernel can shutdown the slot while QEMU is hotplugging it, and this likely ends by an automatic unplug of the card. At the end of the boot sequence the card has disappeared. To fix that, don't set the "Link Active" state in the init function, but rely on the plug function to do it, as the mechanism has already been introduced by 2f2b18f60bf1. Fixes: 2f2b18f60bf1 ("pcie: set link state inactive/active after hot unplug/plug") Cc: zhengxiang9@huawei.com Fixes: 3d67447fe7c2 ("pcie: Fill PCIESlot link fields to support higher speeds and widths") Cc: alex.williamson@redhat.com Fixes: b2101eae63ea ("pcie: Set the "link active" in the link status register") Cc: benh@kernel.crashing.org Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20210212135250.2738750-5-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23failover: really display a warning when the primary device is not foundLaurent Vivier
In failover_add_primary(), we search the id of the failover device by scanning the list of the devices in the opts list to find a device with a failover_pair_id equals to the id of the virtio-net device. If the failover_pair_id is not found, QEMU ignores the primary device silently (which also means it will not be hidden and it will be enabled directly at boot). After that, we search the id in the opts list to do a qdev_device_add() with it. The device will be always found as otherwise we had exited before, and thus the warning is never displayed. Fix that by moving the error report to the first exit condition. Also add a g_assert() to be sure the compiler will not complain about a possibly NULL pointer. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20210212135250.2738750-4-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-23virtio-net: add missing object_unref()Laurent Vivier
failover_add_primary() calls qdev_device_add() and doesn't unref the device. Because of that, when the device is unplugged a reference is remaining and prevents the cleanup of the object. This prevents to be able to plugin back the failover primary device, with errors like: (qemu) device_add vfio-pci,host=0000:41:00.0,id=hostdev0,bus=root.3,failover_pair_id=net0 (qemu) device_del hostdev0 We can check with "info qtree" and "info pci" that the device has been removed, and then: (qemu) device_add vfio-pci,host=0000:41:00.0,id=hostdev1,bus=root.3,failover_pair_id=net0 Error: vfio 0000:41:00.0: device is already attached (qemu) device_add vfio-pci,host=0000:41:00.0,id=hostdev0,bus=root.3,failover_pair_id=net0 qemu-kvm: Duplicate ID 'hostdev0' for device Fixes: 21e8709b29cd ("failover: Remove primary_dev member") Cc: quintela@redhat.com Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20210212135250.2738750-3-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jens Freimann <jfreimann@redhat.com>
2021-02-23pci: cleanup failover sanity checkLaurent Vivier
Commit a1190ab628 has added a "allow_unplug_during_migration = true" at the end of the main "if" block, so it is not needed to set it anymore in the previous checking. Remove it, to have only sub-ifs that check for needed conditions and exit if one fails. Fixes: 4f5b6a05a4e7 ("pci: add option for net failover") Fixes: a1190ab628c0 ("migration: allow unplug during migration for failover devices") Cc: jfreimann@redhat.com Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20210212135250.2738750-2-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jens Freimann <jfreimann@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com>
2021-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/edgar/tags/edgar/cris-next-2021-02-22.for-upstream' into staging CRIS PR 2021-02-22 v1 # gpg: Signature made Mon 22 Feb 2021 08:28:37 GMT # gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown] # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full] # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/cris-next-2021-02-22.for-upstream: target/cris: Plug leakage of TCG temporaries target/cris: Let cris_mmu_translate() use MMUAccessType access_type target/cris: Use MMUAccessType enum type when possible Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-22target/cris: Plug leakage of TCG temporariesStefan Sandstrom
Add and fix deallocation of temporary TCG registers in CRIS code generation. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Change-Id: I17fce5d95bdc4418337ba885d53ba97afb1bafcc Signed-off-by: Stefan Sandström <stefans@axis.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210219124416.28178-1-stefans@axis.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-02-22target/cris: Let cris_mmu_translate() use MMUAccessType access_typePhilippe Mathieu-Daudé
All callers of cris_mmu_translate() provide a MMUAccessType type. Let the prototype use it as argument, as it is stricter than an integer. We can remove the documentation as enum names are self explicit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210128003223.3561108-3-f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-02-22target/cris: Use MMUAccessType enum type when possiblePhilippe Mathieu-Daudé
Replace the 0/1/2 magic values by the corresponding MMUAccessType. We can remove a comment as enum names are self explicit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210128003223.3561108-2-f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2021-02-21Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into ↵Peter Maydell
staging MIPS patches queue - Drop redundant struct MemmapEntry (Bin) - Fix for Coverity CID 1438965 and 1438967 (Jiaxun) - Add MIPS bootloader API (Jiaxun) - Use MIPS bootloader API on fuloong2e and boston machines (Jiaxun) - Add PMON test for Loongson-3A1000 CPU (Jiaxun) - Convert to translator API (Philippe) - MMU cleanups (Philippe) - Promote 128-bit multimedia registers as global ones (Philippe) - Various cleanups/fixes on the VT82C686B southbridge (Zoltan) # gpg: Signature made Sun 21 Feb 2021 18:43:57 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-20210221: (43 commits) vt82c686: Fix superio_cfg_{read,write}() functions vt82c686: Log superio_cfg unimplemented accesses vt82c686: Simplify by returning earlier vt82c686: Reduce indentation by returning early vt82c686: Remove index field of SuperIOConfig vt82c686: Move creation of ISA devices to the ISA bridge vt82c686: Simplify vt82c686b_realize() vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it vt82c686: Set user_creatable=false for VT82C686B_PM vt82c686: Fix up power management io base and config vt82c686: Correctly reset all registers to default values on reset vt82c686: Correct vt82c686-pm I/O size vt82c686: Make vt82c686-pm an I/O tracing region vt82c686: Fix SMBus IO base and configuration registers vt82c686: Reorganise code vt82c686: Move superio memory region to SuperIOConfig struct target/mips: Use GPR move functions in gen_HILO1_tx79() target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers target/mips: Rename 128-bit upper halve GPR registers target/mips: Promote 128-bit multimedia registers as global ones ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-21vt82c686: Fix superio_cfg_{read,write}() functionsBALATON Zoltan
These functions are memory region callbacks so we have to check against relative address not the mapped address. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch in 5, this is part 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Log superio_cfg unimplemented accessesBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch in 5, this is part 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Simplify by returning earlierBALATON Zoltan
By returning earlier we can remove the 'can_write' boolean variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch in 5, this is part 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Reduce indentation by returning earlyBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split patch original in 5, this is part 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Remove index field of SuperIOConfigBALATON Zoltan
Remove the separate index value from SuperIOConfig and store the index at reg 0 which is reserved and returns 0 on read. This simplifies the object state. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch in 5, this is part 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Move creation of ISA devices to the ISA bridgeBALATON Zoltan
Currently the ISA devices that are part of the VIA south bridge, superio chip are wired up by board code. Move creation of these ISA devices to the VIA ISA bridge model so that board code does not need to access ISA bus. This also allows vt82c686b-superio to be made internal to vt82c686 which allows implementing its configuration via registers in subseqent commits. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <bf9400cc8e4ddd3129aa5678de4d3cf38384805f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Simplify vt82c686b_realize()BALATON Zoltan
Remove unneeded variables and setting value to 0 on zero initialised data and replace check for error with error_fatal. Rationalise loop that sets PCI config header fields read only. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <e4caf35ca10a68f5c74ae3f93fa0bcfa9457beea.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on itBALATON Zoltan
The vt82c686b-pm model can be shared between VT82C686B and VT8231. The only difference between the two is the device id in what we emulate so make an abstract via-pm model by renaming appropriately and add types for vt82c686b-pm and vt8231-pm based on it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <34969fc7be984fa070479bfb9f748993a0aef31b.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Set user_creatable=false for VT82C686B_PMBALATON Zoltan
This device is part of the multifunction VIA superio/south bridge chip so not useful in itself. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <d0a806fed5e8055aee4fcf5b2f4790e6dd0f9dc6.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Fix up power management io base and configBALATON Zoltan
Similar to the SMBus io registers there is a power management io range that is set via similar base address reg and enable bit. Some handling of this was already there but with several problems: using the wrong registers and bits, wrong size range, not acually updating mapping and handling reset correctly, nor emulating any of the actual io registers. Some of these errors are fixed up here. After this patch we use the correct base address register, enable bit and region size and allow guests to map/unmap this region, but we still don't emulate any of the registers in this range. PMD notes regarding the Configuration Space Power Management Registers: - 0x40 General Configuration 0 - 0x41 General Configuration 1 . Bit 7: I/O Enable for ACPI I/O Base - 0x48 Power Mgmt I/O Base . Bit 0: Always set . Bits 7-15: Power Management I/O Register Base Address (this explains the change 0xffc0 -> 0xff80) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 4/4, added notes] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Correctly reset all registers to default values on resetBALATON Zoltan
Reset the registers in the DeviceReset() handler which is called on each device reset, not in DeviceRealize() which is called once. Bit 0 of 'Power Mgmt I/O Base' register (offset 0x48) is always set. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch, this is part 3/4 (move to reset), document] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Correct vt82c686-pm I/O sizeBALATON Zoltan
Section "Offset 4B-48 – Power Management I/O Base" describes: Port Address for the base of the 128-byte Power Management I/O Register block. Correct the vt82c686-pm I/O region size. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 2/4, reduced size to 128B] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Make vt82c686-pm an I/O tracing regionBALATON Zoltan
Previously just an empty RAM region was mapped on realize, now we add an empty io range logging access instead. I think the pm timer should be hooked up here but not sure guests need it. PMON on fuloong2e sets a base address but does not seem to enable region; the pegasos2 firmware pokes some regs but continues anyway so don't know if anything would make use of these facilities. Therefore this is just a clean up of previous state for now and not intending to fully implement missing functionality which could be done later if some guests need it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 1/4 (make 'vt82c686-pm' an I/O tracing region)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Fix SMBus IO base and configuration registersBALATON Zoltan
The base address of the SMBus io ports and its enabled status is set by registers in the PCI config space but this was not correctly emulated. Instead the SMBus registers were mapped on realize to the base address set by a property to the address expected by fuloong2e firmware. Fix the base and config register handling to more closely model hardware which allows to remove the property and allows the guest to control this mapping. Do all this in reset instead of realize so it's correctly updated on reset. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <f2ca2ad5f08ba8cee07afd9d67b4e75cda21db09.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Reorganise codeBALATON Zoltan
Move lines around so that object definitions become consecutive and not scattered around. This brings functions belonging to an object together so it's clearer what is defined and what parts belong to which object. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <9f942989dba46fc1c23b881f6cb135948f818c2f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Move superio memory region to SuperIOConfig structBALATON Zoltan
The superio memory region holds the io space index/data registers used to access the superio config registers that are implemented in struct SuperIOConfig. To keep these related things together move the memory region to SuperIOConfig and rename it accordingly. Also remove the unused "data" member of SuperIOConfig which is not needed as we store actual data values in the regs array. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <dc3c4e7632716ca73c10506bd02ee93b39c28705.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé
We have handy functions to access GPR. Use gen_store_gpr() for Move From HI/LO Register and gen_load_gpr() for Move To opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-8-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-7-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé
TCG displays the upper halve registers with the same name as their lower halves. Rename the upper halves with the '[hi]' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-6-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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