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2019-10-28riscv/boot: Fix possible memory leakAlistair Francis
Coverity (CID 1405786) thinks that there is a possible memory leak as we don't guarantee that the memory allocated from riscv_find_firmware() is freed. This is a false positive, but let's tidy up the code to fix the warning. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens
Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that the privilege mode is set to one of them. Once support for the H-extension is added, this code will also need to properly update the virtualization status when switching between VU/VS-modes and M-mode. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens
This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens
If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Jump to pflash if specifiedAlistair Francis
If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis
Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash from the ARM Virt board and the implementation is based on the ARM Virt board. This allows users to specify flash files from the command line. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Manually define the machineAlistair Francis
Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to use the machine object to create RISCVVirtState. This is required to add children and aliases to the machine. This patch is no functional change. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis
Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/sifive_u: Manually define the machineAlistair Francis
Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/sifive_u: Add QSPI memory regionAlistair Francis
The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no model of this in QEMU, so to allow boot firmware developers to use QEMU to target the Unleashed let's add a chunk of memory to represent the QSPI0 memory mapped flash. This can be targeted using QEMU's -device loader command line option. In the future we can look at adding a model for the is25wp256 flash. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis
On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the L2 LIM (LooselyIntegrated Memory). Ideally we would want to adjust the size of this chunk of memory as the L2 Cache Controller WayEnable register is incremented. Unfortunately I don't see a nice way to handle reducing or blocking out the L2 LIM while still allowing it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio
The CPU loop tagged all the queued signals as QEMU_SI_KILL while it was filling the `_sigfault` part of `siginfo`: this caused QEMU to copy the wrong fields over to the userspace program. Make sure the fault address recorded by the MMU is is stored in the CPU environment structure. In case of memory faults store the exception address into `siginfo`. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng
U-Boot expects this alias to be in place in order to fix up the mac address of the ethernet node. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133033/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng
The "clock-frequency" property of cpu nodes isn't required. Drop it. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133031/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
This converts our port over from cpu_do_unassigned_access to cpu_do_transaction_failed, as cpu_do_unassigned_access has been deprecated. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt
We directly access physical memory while walking the page tables on RISC-V, but while doing so we were using cpu_ld*() which does not report bus errors. This patch converts the page table walker over to use address_space_ld*(), which allows bus errors to be detected. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv: Skip checking CSR privilege level in debugger modeBin Meng
If we are in debugger mode, skip the CSR privilege level checking so that we can read/write all CSRs. Otherwise we get: (gdb) p/x $mtvec Could not fetch register "mtvec"; remote failure reply 'E14' when the hart is currently in S-mode. Reported-by: Zong Li <zong.li@sifive.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio: features, tests libqos update with support for virtio 1. Packed ring support for virtio. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 25 Oct 2019 12:47:59 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (25 commits) virtio: drop unused virtio_device_stop_ioeventfd() function libqos: add VIRTIO PCI 1.0 support libqos: extract Legacy virtio-pci.c code libqos: make the virtio-pci BAR index configurable libqos: expose common virtqueue setup/cleanup functions libqos: add MSI-X callbacks to QVirtioPCIDevice libqos: pass full QVirtQueue to set_queue_address() libqos: add iteration support to qpci_find_capability() libqos: access VIRTIO 1.0 vring in little-endian libqos: implement VIRTIO 1.0 FEATURES_OK step libqos: enforce Device Initialization order libqos: add missing virtio-9p feature negotiation tests/virtio-blk-test: set up virtqueue after feature negotiation virtio-scsi-test: add missing feature negotiation libqos: extend feature bits to 64-bit libqos: read QVIRTIO_MMIO_VERSION register tests/virtio-blk-test: read config space after feature negotiation virtio: add property to enable packed virtqueue vhost_net: enable packed ring support virtio: event suppression support for packed ring ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Bulgarian translation update (Alexander) * RTC and PC refactorings (Hervé, Philippe, Sergio) * RTC fix (Marcelo) * More comprehensive MCE logging (Mario) * x86 IGNNE implementation (Paolo) * Microvm machine type (Sergio) * Support for UMONITOR/UMWAIT/TPAUSE (Tao) * Do not use %m in common code (Thomas) * NoNonArchitecturalCoreSharing Hyper-V enlightenment (Vitaly) * getpagesize cleanups (Wei) # gpg: Signature made Sat 26 Oct 2019 14:39:56 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (39 commits) i386: implement IGNNE target/i386: introduce cpu_set_fpus target/i386: move FERR handling to target/i386 core: replace getpagesize() with qemu_real_host_page_size audio: fix missing break mc146818rtc: always register rtc to rtc list mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c mc146818rtc: Move RTC_ISA_IRQ definition mc146818rtc: move structure to header file hw/i386/pc: Remove kvm_i386.h include hw/i386/pc: Extract pc_i8259_create() hw/i386/pc: Move gsi_state creation code hw/i386/pc: Extract pc_gsi_create() target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE hw/timer/mc146818rtc: Only include qapi-commands-misc on I386 runstate: ignore exit request in finish migrate state checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE) MAINTAINERS: add microvm related files hw/i386: Introduce the microvm machine type ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-26i386: implement IGNNEPaolo Bonzini
Change the handling of port F0h writes and FPU exceptions to implement IGNNE. The implementation mixes a bit what the chipset and processor do in real hardware, but the effect is the same as what happens with actual FERR# and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26target/i386: introduce cpu_set_fpusPaolo Bonzini
In the next patch, this will provide a hook to detect clearing of FSW.ES. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26target/i386: move FERR handling to target/i386Paolo Bonzini
Move it out of pc.c since it is strictly tied to TCG. This is almost exclusively code movement, the next patch will implement IGNNE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26core: replace getpagesize() with qemu_real_host_page_sizeWei Yang
There are three page size in qemu: real host page size host page size target page size All of them have dedicate variable to represent. For the last two, we use the same form in the whole qemu project, while for the first one we use two forms: qemu_real_host_page_size and getpagesize(). qemu_real_host_page_size is defined to be a replacement of getpagesize(), so let it serve the role. [Note] Not fully tested for some arch or device. Signed-off-by: Wei Yang <richardw.yang@linux.intel.com> Message-Id: <20191013021145.16011-3-richardw.yang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26audio: fix missing breakPaolo Bonzini
Reported by Coverity (CID 1406449). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26Merge commit 'df84f17' into HEADPaolo Bonzini
This merge fixes a semantic conflict with the trivial tree. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-next-251019-3' into staging Testing updates (split from mega PR) - various Travis dependency updates - enable tcg debug for check-tcg - additional Xcode build for Cirrus - dependency tweak for gitlab # gpg: Signature made Fri 25 Oct 2019 20:35:56 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-next-251019-3: tests/docker: update Travis image to a more current version tests/docker: set HOST_ARCH if we don't have ARCH travis.yml: --enable-debug-tcg to check-tcg gitlab-ci.yml: Use libvdeplug-dev to compile-test the VDE network backend travis.yml: cache the clang sanitizer build tests/vm/netbsd: Disable IPv6 tests/vm: Let subclasses disable IPv6 cirrus.yml: add latest Xcode build target travis.yml: bump Xcode 10 to latest dot release travis.yml: Test the release tarball travis.yml: Fix the ccache lines travis.yml: Use newer version of libgnutls and libpng travis.yml: Use libsdl2 instead of libsdl1.2, and install libsdl2-image travis.yml: Add libvdeplug-dev to compile-test net/vde.c travis.yml: reduce scope of the --enable-debug build Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-25Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request # gpg: Signature made Fri 25 Oct 2019 20:18:23 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: yield_until_fd_readable: make it work with any AioContect virtio-blk: Add blk_drain() to virtio_blk_device_unrealize() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-25tests/docker: update Travis image to a more current versionAlex Bennée
This isn't the latest one available on hub.docker.com but it does match the ID reported by the Xenial builds running on Travis: instance: ... travis-ci-sardonyx-xenial-1553530528-f909ac5 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25tests/docker: set HOST_ARCH if we don't have ARCHAlex Bennée
As the docker rules want to be able to be run on a virgin unconfigured checkout add a fallback and use it if we need to. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: --enable-debug-tcg to check-tcgAlex Bennée
This adds a whole bunch of asserts which will catch bugs you might introduce into the TCG code. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-25gitlab-ci.yml: Use libvdeplug-dev to compile-test the VDE network backendThomas Huth
The libvdeplug-dev package is required to compile-test net/vde.c. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191016131002.29663-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: cache the clang sanitizer buildAlex Bennée
Hopefully we'll see the same benefits as the other builds. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-25tests/vm/netbsd: Disable IPv6Eduardo Habkost
Workaround for issues when the host has no IPv6 connectivity. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191018181705.17957-4-ehabkost@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25tests/vm: Let subclasses disable IPv6Eduardo Habkost
The mechanism will be used to work around issues related to IPv6 on the netbsd image builder. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191018181705.17957-3-ehabkost@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25cirrus.yml: add latest Xcode build targetAlex Bennée
CirrusCI provides a mojave-xcode alias for the latest Xcode available. Let's use it to make sure we track the latest releases. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: bump Xcode 10 to latest dot releaseAlex Bennée
According to: https://docs.travis-ci.com/user/reference/osx/#macos-version we have 10.3 available so lets use it. I don't know what Apple's deprecation policy is for Xcode because it requires an AppleID to find out. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-25travis.yml: Test the release tarballPhilippe Mathieu-Daudé
Add a job to generate the release tarball and build/install few QEMU targets from it. Ideally we should build the 'efi' target from the 'roms' directory, but it is too time consuming. This job is only triggered when a tag starting with 'v' is pushed, which is the case with release candidate tags. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191007160450.3619-1-philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: Fix the ccache linesThomas Huth
The "command -v ccache && ccache ..." likely were supposed to test the availability of ccache before running the program. But this shell construct causes Travis to abort if ccache is not available. Use an if-statement instead to fix this problem. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191009170701.14756-5-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: Use newer version of libgnutls and libpngThomas Huth
libgnutls-dev and libpng12-dev are not available in newer versions of Ubuntu anymore, so installing these packages fails e.g. in the new arm64 containers on Travis. Let's use newer versions of these packages by default instead. (The old versions still get tested in the "gcc-9" build). Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191009170701.14756-4-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: Use libsdl2 instead of libsdl1.2, and install libsdl2-imageThomas Huth
We've removed support for SDL 1.2 quite a while ago already, so let's use SDL 2 now in Travis to get test coverage for SDL again. And while we're at it, also add libsdl2-image-dev which can be used by QEMU nowadays, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191009170701.14756-3-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-25travis.yml: Add libvdeplug-dev to compile-test net/vde.cThomas Huth
This library is needed to compile the VDE network backend. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191009170701.14756-2-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-25travis.yml: reduce scope of the --enable-debug buildAlex Bennée
Adding debug makes things run a bit slower so lets not hammer all the targets. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-25Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-oct-24-2019-v2' into staging MIPS queue for October 24th, 2019 - v2 # gpg: Signature made Fri 25 Oct 2019 17:37:29 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-24-2019-v2: tests/ssh_linux_malta: Fix 64-bit target tests tests/ssh_linux_malta: Refactor how to get image/kernel info tests/ssh_linux_malta: Match stricter console output tests/ssh_linux_malta: Remove duplicated test tests/ssh_linux_malta: Run tests using a snapshot image target/mips: Refactor handling of vector compare 'less than' (signed) instructions target/mips: Refactor handling of vector compare 'equal' instructions target/mips: Demacro LMI decoder target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D> target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D> target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D> target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D> target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D> target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D> target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D> MAINTAINERS: Update mail address of Aleksandar Rikalo target/mips: Clean up op_helper.c target/mips: Clean up helper.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-25tests/ssh_linux_malta: Fix 64-bit target testsPhilippe Mathieu-Daudé
Commit 9090d3332cdcc added tests for specific to the 32-bit machines, which inadvertently make the 64-bit tests failing. Now than we have this information available in the CPU_INFO array, use it to have the 64-bit tests back. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20191019153437.9820-12-f4bug@amsat.org>
2019-10-25tests/ssh_linux_malta: Refactor how to get image/kernel infoPhilippe Mathieu-Daudé
The qcow and kernel images use a similar pattern regarding they are for big/little endianess, or 32/64 bit. Refactor using more dictionary keys. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20191019153437.9820-11-f4bug@amsat.org>
2019-10-25tests/ssh_linux_malta: Match stricter console outputPhilippe Mathieu-Daudé
Match on stricter console output. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20191019153437.9820-10-f4bug@amsat.org>
2019-10-25tests/ssh_linux_malta: Remove duplicated testPhilippe Mathieu-Daudé
Remove duplicated test (probably copy/paste error in commit 9090d3332cdcc). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20191019153437.9820-9-f4bug@amsat.org>
2019-10-25tests/ssh_linux_malta: Run tests using a snapshot imagePhilippe Mathieu-Daudé
If a test fails, it can corrupt the underlying QCow2 image, making further tests failing. Fix this by running each test with a snapshot. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20191019153437.9820-8-f4bug@amsat.org>
2019-10-25target/mips: Refactor handling of vector compare 'less than' (signed) ↵Filip Bozuta
instructions Remove unnecessary argument and provide separate function for each instruction. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571837825-24438-3-git-send-email-Filip.Bozuta@rt-rk.com>
2019-10-25target/mips: Refactor handling of vector compare 'equal' instructionsFilip Bozuta
Remove unnecessary argument and provide separate function for each instruction. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571837825-24438-2-git-send-email-Filip.Bozuta@rt-rk.com>