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2019-06-10Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190607-pull-request' ↵Peter Maydell
into staging usb-mtp: refactor the flow of usb_mtp_write_data # gpg: Signature made Fri 07 Jun 2019 17:56:31 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20190607-pull-request: usb-mtp: refactor the flow of usb_mtp_write_data Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-10Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine Core queue, 2019-06-07 * Improve CPU hotplug error message (Laurent Vivier) * Remove unused AccelClass::opt_name field (Wainer dos Santos Moschetta) # gpg: Signature made Fri 07 Jun 2019 19:31:28 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: accel: Remove unused AccelClass::opt_name attribute numa: improve cpu hotplug error message with a wrong node-id Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07accel: Remove unused AccelClass::opt_name attributeWainer dos Santos Moschetta
The AccelType type was converted to AccelClass QOM object on b14a0b7469f, and the original data type had a field to store the option name which in turn was used to search an accelerator. The lookup method (accel_find) changed too, making the option field unnecessary but it became AccelClass::opt_name despite that. Therefore, and given that none accelerator implementation sets AccelClass::opt_name, let's remove this attribute. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20190531165334.20403-2-wainersm@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-06-07numa: improve cpu hotplug error message with a wrong node-idLaurent Vivier
On pseries, core-ids are strongly binded to a node-id by the command line option. If an user tries to add a CPU to the wrong node, he has an error but it is not really helpful: qemu-system-ppc64 ... -smp 1,maxcpus=64,cores=1,threads=1,sockets=1 \ -numa node,nodeid=0 -numa node,nodeid=1 ... (qemu) device_add power9_v2.0-spapr-cpu-core,core-id=30,node-id=1 Error: node-id=1 must match numa node specified with -numa option This patch improves this error message by giving to the user the good node-id to use with the core-id he's providing Error: invalid node-id, must be 0 Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190529160747.778-1-lvivier@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-06-07usb-mtp: refactor the flow of usb_mtp_write_dataBandan Das
There's no functional change but the flow is (hopefully) more consistent for both file and folder object types. Signed-off-by: Bandan Das <bsd@redhat.com> Message-Id: <20190401211712.19012-4-bsd@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-06-07Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190607-2' into stagingPeter Maydell
s390x updates: - tcg: finalize implementation for the vector facility and add it to the 'qemu' cpu model - linux-user: properly generate ELF_HWCAP # gpg: Signature made Fri 07 Jun 2019 15:14:42 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190607-2: (34 commits) linux-user: elf: ELF_HWCAP for s390x s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT s390x: Bump the "qemu" CPU model up to a stripped-down z13 s390x/tcg: We support the Vector Facility s390x/tcg: Allow linux-user to use vector instructions s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE s390x/tcg: Implement VECTOR FP SUBTRACT s390x/tcg: Implement VECTOR FP SQUARE ROOT s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) s390x/tcg: Implement VECTOR FP MULTIPLY s390x/tcg: Implement VECTOR LOAD ROUNDED s390x/tcg: Implement VECTOR LOAD LENGTHENED s390x/tcg: Implement VECTOR LOAD FP INTEGER s390x/tcg: Implement VECTOR FP DIVIDE s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07Merge tag 's390x-tcg-2019-06-07' into s390-next-stagingCornelia Huck
Finalize implementation of the "Vector Facility" for s390x TCG. Add it to the QEMU CPU model, so it is enabled as default. Also: - One fix (and one workaround) for the STFLE instruction - Fix the alignment of vector registers (and change the data type) - Properly generate ELF_HWCAP for s390x for linux-user - Use a gvec helper for VECTOR SELECT # gpg: Signature made Fri 07 Jun 2019 02:58:01 PM CEST # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-06-07': (33 commits) linux-user: elf: ELF_HWCAP for s390x s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT s390x: Bump the "qemu" CPU model up to a stripped-down z13 s390x/tcg: We support the Vector Facility s390x/tcg: Allow linux-user to use vector instructions s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE s390x/tcg: Implement VECTOR FP SUBTRACT s390x/tcg: Implement VECTOR FP SQUARE ROOT s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) s390x/tcg: Implement VECTOR FP MULTIPLY s390x/tcg: Implement VECTOR LOAD ROUNDED s390x/tcg: Implement VECTOR LOAD LENGTHENED s390x/tcg: Implement VECTOR LOAD FP INTEGER s390x/tcg: Implement VECTOR FP DIVIDE s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) ... Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-07Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190607-pull-request' ↵Peter Maydell
into staging curses: 32bit build fix. egl: dmabuf modifier support. # gpg: Signature made Fri 07 Jun 2019 14:18:41 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20190607-pull-request: egl-helpers: add modifier support to egl_dmabuf_import_texture() egl-helpers: add modifier support to egl_get_fd_for_texture(). vfio/display: set dmabuf modifier field console: add dmabuf modifier field. ui/curses: Fix build with -m32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07linux-user: elf: ELF_HWCAP for s390xDavid Hildenbrand
Let's add all HWCAPs that we can support under TCG right now, when the respective CPU facilities are enabled. Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Cornelia Huck <cohuck@redhat.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Richard Henderson <richard.henderson@linaro.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECTRichard Henderson
This replaces the target-specific implementations for VSEL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Bump the "qemu" CPU model up to a stripped-down z13David Hildenbrand
We don't care about the other two missing base features: - S390_FEAT_DFP_PACKED_CONVERSION - S390_FEAT_GROUP_GEN13_PTFF Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: We support the Vector FacilityDavid Hildenbrand
Let's add it to the max model, so we can enable it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Allow linux-user to use vector instructionsDavid Hildenbrand
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be able to make use of it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand
We can reuse float64_dcmask(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand
Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand
The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand
Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand
We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand
Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand
We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand
We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand
1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand
Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand
As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand
1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()David Hildenbrand
Vector floating-point instructions will require these functions, so allow to use them from other files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Introduce tcg_s390_vector_exception()David Hildenbrand
Handling is similar to data exceptions, however we can always store the VXC into the lowore and the FPC: z14 PoP, 6-20, "Vector-Exception Code" When a vector-processing exception causes a pro- gram interruption, a vector-exception code (VXC) is stored at location 147, and zeros are stored at loca- tions 144-146. The VXC is also placed in the DXC field of the floating-point-control (FPC) register if bit 45 of control register 0 is one. When bit 45 of control register 0 is zero and bit 46 of control register 0 is one, the DXC field of the FPC register and the con- tents of storage at location 147 are unpredictable. Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Store only the necessary amount of doublewords for STFLEDavid Hildenbrand
The PoP (z14, 7-382) says: Doublewords to the right of the doubleword in which the highest-numbered facility bit is assigned for a model may or may not be stored. However, stack protection in certain binaries can't deal with that. "gzip" example code: f1b4: a7 08 00 03 lhi %r0,3 f1b8: b2 b0 f0 a0 stfle 160(%r15) f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15) f1c2: c0 2b 00 00 00 01 nilf %r2,1 f1c8: b2 4f 00 10 ear %r1,%a0 f1cc: b9 14 00 22 lgfr %r2,%r2 f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32 f1d6: b2 4f 00 11 ear %r1,%a1 f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1) f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc> f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15) f1ea: 07 fe br %r14 f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt> In QEMU, we currently have: max_bytes = 24 the code asks for (3 + 1) doublewords == 32 bytes. If we write 32 bytes instead of only 24, and return "2 + 1" doublewords ("one less than the number of doulewords needed to contain all of the facility bits"), the example code detects a stack corruption. In my opinion, the code is wrong. However, it seems to work fine on real machines. So let's limit storing to the minimum of the requested and the maximum doublewords. Cc: Stefan Liebler <stli@linux.ibm.com> Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Fix max_byte detection for stfleDavid Hildenbrand
used_stfl_bytes is 0, before initialized via prepare_stfl() on the first invocation. We have to move the calculation of max_bytes after prepare_stfl(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Use uint64_t for vector registersDavid Hildenbrand
CPU_DoubleU is primarily used to reinterpret between integer and floats. We don't really need this functionality. So let's just keep it simple and use an uint64_t. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Align vector registers to 16 bytesDavid Hildenbrand
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store") revealed that the vregs are not aligned to 16 bytes. Align them to 16 bytes, to avoid segfault'ing on x86. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand
Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand
Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand
Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand
Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07MAINTAINERS: cover tests/migration/s390x/Cornelia Huck
The generic s390 section looks like the best resting place. Message-Id: <20190529091243.25562-1-cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-07Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-7-2019' ↵Peter Maydell
into staging MIPS Queue for June 7th, 2019 # gpg: Signature made Fri 07 Jun 2019 10:59:15 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-7-2019: tests/tcg: target/mips: Add README for MSA tests tests/tcg: target/mips: Add tests for MSA FP max/min instructions tests/tcg: target/mips: Add utility function reset_msa_registers() tests/tcg: target/mips: Move four tests to a better location tests/tcg: target/mips: Add tests for MSA shift instructions tests/tcg: target/mips: Amend and rearrange MSA wrappers target/mips: Unroll loops in helpers for MSA logic instructions target/mips: Outline places for future MSA helpers target/mips: Fix block-comment-related issues in msa_helper.c target/mips: Fix space-related format issues in msa_helper.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07tests/tcg: target/mips: Add README for MSA testsAleksandar Markovic
Add README for MSA tests. This is just to explain how to run tests even without Makefile. Makefile will be provided later on. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add tests for MSA FP max/min instructionsAleksandar Markovic
Add tests for MSA FP max/min instructions. This includes following instructions: * FMAX.W - float maximum (words) * FMAX.D - float maximum (doublewords) * FMAX_A.W - float maximum absolute (words) * FMAX_A.D - float maximum absolute (doublewords) * FMIN.W - float minimum (words) * FMIN.D - float minimum (doublewords) * FMIN_A.W - float minimum absolute (words) * FMIN_A.D - float minimum absolute (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add utility function reset_msa_registers()Aleksandar Markovic
Add function reset_msa_registers() and utilize it in each MSA test. This is needed to ensure independency of test results on the state of MSA registers before test execution. This also allows for correction of tests for VSHF* instructions, that are now independent on the previous state of MSA registers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Move four tests to a better locationAleksandar Markovic
Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory to "fixed-point multiply" directory, since they do not operate on integers, but on fixed point numbers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add tests for MSA shift instructionsAleksandar Markovic
Add tests for MSA shift instructions. This includes following instructions: * SLL.B - shift left logical (bytes) * SLL.H - shift left logical (halfwords) * SLL.W - shift left logical (words) * SLL.D - shift left logical (doublewords) * SRA.B - shift right arithmetic (bytes) * SRA.H - shift right arithmetic (halfwords) * SRA.W - shift right arithmetic (words) * SRA.D - shift right arithmetic (doublewords) * SRAR.B - shift right arithmetic rounded (bytes) * SRAR.H - shift right arithmetic rounded (halfwords) * SRAR.W - shift right arithmetic rounded (words) * SRAR.D - shift right arithmetic rounded (doublewords) * SRL.B - shift right logical (bytes) * SRL.H - shift right logical (halfwords) * SRL.W - shift right logical (words) * SRL.D - shift right logical (doublewords) * SRLR.B - shift right logical rounded (bytes) * SRLR.H - shift right logical rounded (halfwords) * SRLR.W - shift right logical rounded (words) * SRLR.D - shift right logical rounded (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Amend and rearrange MSA wrappersAleksandar Markovic
Amend and rearrange MSA wrappers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07target/mips: Unroll loops in helpers for MSA logic instructionsAleksandar Markovic
Unroll loops in helpers for MSA logic instructions for better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
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