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-rw-r--r--target/riscv/cpu.c1
-rw-r--r--target/riscv/cpu.h1
-rw-r--r--target/riscv/csr.c17
3 files changed, 14 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a54ebf10c..be90fa7d08 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -440,6 +440,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0855277b92..4d4e0f89e2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -222,6 +222,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_counters;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 448162e484..de67741f36 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,17 +56,24 @@ static int fs(CPURISCVState *env, int csrno)
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ uint32_t ctr_en = ~0u;
+
+ if (!cpu->cfg.ext_counters) {
+ /* The Counters extensions is not enabled */
+ return -1;
+ }
+
/*
- * The counters are always enabled on newer priv specs, as the CSR has
- * changed from controlling that the counters can be read to controlling
- * that the counters increment.
+ * The counters are always enabled at run time on newer priv specs, as the
+ * CSR has changed from controlling that the counters can be read to
+ * controlling that the counters increment.
*/
if (env->priv_ver > PRIV_VERSION_1_09_1) {
return 0;
}
- uint32_t ctr_en = ~0u;
-
if (env->priv < PRV_M) {
ctr_en &= env->mcounteren;
}