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-rw-r--r--target/arm/cpu.c50
-rw-r--r--target/arm/cpu64.c59
2 files changed, 55 insertions, 54 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2292ad91f6..022d8c5787 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -970,9 +970,19 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
ObjectClass *oc;
char *typename;
char **cpuname;
+ const char *cpunamestr;
cpuname = g_strsplit(cpu_model, ",", 1);
- typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);
+ cpunamestr = cpuname[0];
+#ifdef CONFIG_USER_ONLY
+ /* For backwards compatibility usermode emulation allows "-cpu any",
+ * which has the same semantics as "-cpu max".
+ */
+ if (!strcmp(cpunamestr, "any")) {
+ cpunamestr = "max";
+ }
+#endif
+ typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
@@ -1716,29 +1726,23 @@ static void arm_max_initfn(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
} else {
cortex_a15_initfn(obj);
- /* In future we might add feature bits here even if the
- * real-world A15 doesn't implement them.
+#ifdef CONFIG_USER_ONLY
+ /* We don't set these in system emulation mode for the moment,
+ * since we don't correctly set the ID registers to advertise them,
*/
- }
-}
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
#endif
-
-#ifdef CONFIG_USER_ONLY
-static void arm_any_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
- set_feature(&cpu->env, ARM_FEATURE_CRC);
- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
- cpu->midr = 0xffffffff;
+ }
}
#endif
@@ -1794,7 +1798,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "max", .initfn = arm_max_initfn },
#endif
#ifdef CONFIG_USER_ONLY
- { .name = "any", .initfn = arm_any_initfn },
+ { .name = "any", .initfn = arm_max_initfn },
#endif
#endif
{ .name = NULL }
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 89b2f4eaed..991d764674 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -228,38 +228,38 @@ static void aarch64_max_initfn(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
} else {
aarch64_a57_initfn(obj);
- /* In future we might add feature bits here even if the
- * real-world A57 doesn't implement them.
+#ifdef CONFIG_USER_ONLY
+ /* We don't set these in system emulation mode for the moment,
+ * since we don't correctly set the ID registers to advertise them,
+ * and in some cases they're only available in AArch64 and not AArch32,
+ * whereas the architecture requires them to be present in both if
+ * present in either.
+ */
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
+ /* For usermode -cpu max we can use a larger and more efficient DCZ
+ * blocksize since we don't have to follow what the hardware does.
*/
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
+ cpu->dcz_blocksize = 7; /* 512 bytes */
+#endif
}
}
-#ifdef CONFIG_USER_ONLY
-static void aarch64_any_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
- set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
- set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
- set_feature(&cpu->env, ARM_FEATURE_CRC);
- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
- set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
- cpu->dcz_blocksize = 7; /* 512 bytes */
-}
-#endif
-
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
@@ -270,9 +270,6 @@ static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
-#ifdef CONFIG_USER_ONLY
- { .name = "any", .initfn = aarch64_any_initfn },
-#endif
{ .name = NULL }
};