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-rw-r--r--target-mips/op.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/op.c b/target-mips/op.c
index cd5c69ca46..34c17c1ab5 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1340,7 +1340,7 @@ void op_mtc0_entryhi (void)
/* 1k pages not implemented */
/* Ignore MIPS64 TLB for now */
- val = (int32_t)T0 & 0xFFFFE0FF;
+ val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
old = env->CP0_EntryHi;
env->CP0_EntryHi = val;
/* If the ASID changes, flush qemu's TLB. */