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-rw-r--r--target-i386/helper.c16
-rw-r--r--target-i386/helper2.c13
2 files changed, 26 insertions, 3 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index b2c829926c..c3d307eeb4 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1747,7 +1747,21 @@ void helper_cpuid(void)
break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
- EAX = 0x00003028;
+/* XXX: This value must match the one used in the MMU code. */
+#if defined(TARGET_X86_64)
+# if defined(USE_KQEMU)
+ EAX = 0x00003020; /* 48 bits virtual, 32 bits physical */
+# else
+/* XXX: The physical address space is limited to 42 bits in exec.c. */
+ EAX = 0x00003028; /* 48 bits virtual, 40 bits physical */
+# endif
+#else
+# if defined(USE_KQEMU)
+ EAX = 0x00000020; /* 32 bits physical */
+# else
+ EAX = 0x00000024; /* 36 bits physical */
+# endif
+#endif
EBX = 0;
ECX = 0;
EDX = 0;
diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index 106720aa7f..6cf218fa0d 100644
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -800,8 +800,17 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
#else
-/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
-#define PHYS_ADDR_MASK 0xffffffffff000L
+/* XXX: This value should match the one returned by CPUID
+ * and in exec.c */
+#if defined(USE_KQEMU)
+#define PHYS_ADDR_MASK 0xfffff000L
+#else
+# if defined(TARGET_X86_64)
+# define PHYS_ADDR_MASK 0xfffffff000L
+# else
+# define PHYS_ADDR_MASK 0xffffff000L
+# endif
+#endif
/* return value:
-1 = cannot handle fault