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-rw-r--r--include/hw/mips/cps.h2
-rw-r--r--include/hw/misc/mips_cmgcr.h9
2 files changed, 11 insertions, 0 deletions
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 4dbae9c8c9..526b8d0b11 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -22,6 +22,7 @@
#include "hw/sysbus.h"
#include "hw/misc/mips_cmgcr.h"
+#include "hw/intc/mips_gic.h"
#include "hw/misc/mips_cpc.h"
#include "hw/misc/mips_itu.h"
@@ -37,6 +38,7 @@ typedef struct MIPSCPSState {
MemoryRegion container;
MIPSGCRState gcr;
+ MIPSGICState gic;
MIPSCPCState cpc;
MIPSITUState itu;
} MIPSCPSState;
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
index cc60eefa53..5b90e948b5 100644
--- a/include/hw/misc/mips_cmgcr.h
+++ b/include/hw/misc/mips_cmgcr.h
@@ -26,7 +26,9 @@
#define GCR_CONFIG_OFS 0x0000
#define GCR_BASE_OFS 0x0008
#define GCR_REV_OFS 0x0030
+#define GCR_GIC_BASE_OFS 0x0080
#define GCR_CPC_BASE_OFS 0x0088
+#define GCR_GIC_STATUS_OFS 0x00D0
#define GCR_CPC_STATUS_OFS 0x00F0
#define GCR_L2_CONFIG_OFS 0x0130
@@ -38,6 +40,11 @@
#define GCR_L2_CONFIG_BYPASS_SHF 20
#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
+/* GCR_GIC_BASE register fields */
+#define GCR_GIC_BASE_GICEN_MSK 1
+#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
+#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
+
/* GCR_CPC_BASE register fields */
#define GCR_CPC_BASE_CPCEN_MSK 1
#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
@@ -52,8 +59,10 @@ struct MIPSGCRState {
hwaddr gcr_base;
MemoryRegion iomem;
MemoryRegion *cpc_mr;
+ MemoryRegion *gic_mr;
uint64_t cpc_base;
+ uint64_t gic_base;
};
#endif /* _MIPS_GCR_H */