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-rw-r--r--include/exec/cpu-all.h5
-rw-r--r--include/hw/arm/omap.h30
-rw-r--r--include/hw/arm/smmu-common.h24
-rw-r--r--include/hw/arm/smmuv3.h1
-rw-r--r--include/hw/misc/aspeed_scu.h70
-rw-r--r--include/hw/ssi/xilinx_spips.h5
-rw-r--r--include/hw/timer/aspeed_timer.h4
7 files changed, 109 insertions, 30 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 7fa726b8e3..7338f57062 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -330,11 +330,14 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3))
+/* Set if TLB entry must have MMU lookup repeated for every access */
+#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4))
/* Use this mask to check interception with an alignment mask
* in a TCG backend.
*/
-#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO)
+#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
+ | TLB_RECHECK)
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index b398607b06..e7fbd340f3 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -21,6 +21,7 @@
# define hw_omap_h "omap.h"
#include "hw/irq.h"
#include "target/arm/cpu-qom.h"
+#include "qemu/log.h"
# define OMAP_EMIFS_BASE 0x00000000
# define OMAP2_Q0_BASE 0x00000000
@@ -944,8 +945,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core);
-#define OMAP_FMT_plx "%#08" HWADDR_PRIx
-
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value);
@@ -959,11 +958,12 @@ void omap_badwidth_write32(void *opaque, hwaddr addr,
void omap_mpu_wakeup(void *opaque, int irq, int req);
# define OMAP_BAD_REG(paddr) \
- fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
- __func__, paddr)
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
+ __func__, paddr)
# define OMAP_RO_REG(paddr) \
- fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
- __func__, paddr)
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
+ HWADDR_PRIx "\n", \
+ __func__, paddr)
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
(Board-specifc tags are not here) */
@@ -993,24 +993,6 @@ enum {
#define OMAP_GPIOSW_INVERTED 0x0001
#define OMAP_GPIOSW_OUTPUT 0x0002
-# define TCMI_VERBOSE 1
-
-# ifdef TCMI_VERBOSE
-# define OMAP_8B_REG(paddr) \
- fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
- __func__, paddr)
-# define OMAP_16B_REG(paddr) \
- fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
- __func__, paddr)
-# define OMAP_32B_REG(paddr) \
- fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
- __func__, paddr)
-# else
-# define OMAP_8B_REG(paddr)
-# define OMAP_16B_REG(paddr)
-# define OMAP_32B_REG(paddr)
-# endif
-
# define OMAP_MPUI_REG_MASK 0x000007ff
#endif /* hw_omap_h */
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index c41eb5c3b0..50e2912a95 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -67,6 +67,8 @@ typedef struct SMMUTransCfg {
uint8_t tbi; /* Top Byte Ignore */
uint16_t asid;
SMMUTransTableInfo tt[2];
+ uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
+ uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
} SMMUTransCfg;
typedef struct SMMUDevice {
@@ -75,6 +77,8 @@ typedef struct SMMUDevice {
int devfn;
IOMMUMemoryRegion iommu;
AddressSpace as;
+ uint32_t cfg_cache_hits;
+ uint32_t cfg_cache_misses;
} SMMUDevice;
typedef struct SMMUNotifierNode {
@@ -87,6 +91,11 @@ typedef struct SMMUPciBus {
SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
} SMMUPciBus;
+typedef struct SMMUIOTLBKey {
+ uint64_t iova;
+ uint16_t asid;
+} SMMUIOTLBKey;
+
typedef struct SMMUState {
/* <private> */
SysBusDevice dev;
@@ -142,4 +151,19 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
*/
SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
+/* Return the iommu mr associated to @sid, or NULL if none */
+IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
+
+#define SMMU_IOTLB_MAX_SIZE 256
+
+void smmu_iotlb_inv_all(SMMUState *s);
+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
+void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);
+
+/* Unmap the range of all the notifiers registered to any IOMMU mr */
+void smmu_inv_notifiers_all(SMMUState *s);
+
+/* Unmap the range of all the notifiers registered to @mr */
+void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
+
#endif /* HW_ARM_SMMU_COMMON */
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index 23f70363e5..36b2f45253 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -59,6 +59,7 @@ typedef struct SMMUv3State {
SMMUQueue eventq, cmdq;
qemu_irq irq[4];
+ QemuMutex mutex;
} SMMUv3State;
typedef enum {
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d70cc0aeca..f662c38188 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -30,6 +30,10 @@ typedef struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
+
+ uint32_t clkin;
+ uint32_t hpll;
+ uint32_t apb_freq;
} AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U
@@ -58,7 +62,64 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
* 1. 2012/12/29 Ryan Chen Create
*/
-/* Hardware Strapping Register definition (for Aspeed AST2400 SOC)
+/* SCU08 Clock Selection Register
+ *
+ * 31 Enable Video Engine clock dynamic slow down
+ * 30:28 Video Engine clock slow down setting
+ * 27 2D Engine GCLK clock source selection
+ * 26 2D Engine GCLK clock throttling enable
+ * 25:23 APB PCLK divider selection
+ * 22:20 LPC Host LHCLK divider selection
+ * 19 LPC Host LHCLK clock generation/output enable control
+ * 18:16 MAC AHB bus clock divider selection
+ * 15 SD/SDIO clock running enable
+ * 14:12 SD/SDIO divider selection
+ * 11 Reserved
+ * 10:8 Video port output clock delay control bit
+ * 7 ARM CPU/AHB clock slow down enable
+ * 6:4 ARM CPU/AHB clock slow down setting
+ * 3:2 ECLK clock source selection
+ * 1 CPU/AHB clock slow down idle timer
+ * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
+ */
+#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
+
+/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
+ *
+ * 18 H-PLL parameter selection
+ * 0: Select H-PLL by strapping resistors
+ * 1: Select H-PLL by the programmed registers (SCU24[17:0])
+ * 17 Enable H-PLL bypass mode
+ * 16 Turn off H-PLL
+ * 10:5 H-PLL Numerator
+ * 4 H-PLL Output Divider
+ * 3:0 H-PLL Denumerator
+ *
+ * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
+ */
+
+#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
+#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
+#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
+
+/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
+ *
+ * 21 Enable H-PLL reset
+ * 20 Enable H-PLL bypass mode
+ * 19 Turn off H-PLL
+ * 18:13 H-PLL Post Divider
+ * 12:5 H-PLL Numerator (M)
+ * 4:0 H-PLL Denumerator (N)
+ *
+ * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
+ *
+ * The default frequency is 792Mhz when CLKIN = 24MHz
+ */
+
+#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
+#define SCU_H_PLL_OFF (0x1 << 19)
+
+/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
*
* 31:29 Software defined strapping registers
* 28:27 DRAM size setting (for VGA driver use)
@@ -107,12 +168,13 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
| (((x) >> 18) & 0x1))
#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
-#define AST2400_CLK_25M_IN (0x1 << 23)
+#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
#define AST2400_CLK_24M_IN 0
#define AST2400_CLK_48M_IN 1
#define AST2400_CLK_25M_IN_24M_USB_CKI 2
#define AST2400_CLK_25M_IN_48M_USB_CKI 3
+#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
@@ -160,8 +222,8 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define AST2400_DIS_BOOT 3
/*
- * Hardware strapping register definition (for Aspeed AST2500 SoC and
- * higher)
+ * SCU70 Hardware strapping register definition (for Aspeed AST2500
+ * SoC and higher)
*
* 31 Enable SPI Flash Strap Auto Fetch Mode
* 30 Enable GPIO Strap Mode
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index d398a4e81c..a0a0ae7584 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -37,6 +37,8 @@ typedef struct XilinxSPIPS XilinxSPIPS;
/* Bite off 4k chunks at a time */
#define LQSPI_CACHE_SIZE 1024
+#define QSPI_DMA_MAX_BURST_SIZE 2048
+
typedef enum {
READ = 0x3, READ_4 = 0x13,
FAST_READ = 0xb, FAST_READ_4 = 0x0c,
@@ -95,7 +97,6 @@ typedef struct {
XilinxQSPIPS parent_obj;
StreamSlave *dma;
- uint8_t dma_buf[4];
int gqspi_irqline;
uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
@@ -113,6 +114,8 @@ typedef struct {
uint8_t rx_fifo_g_align;
uint8_t tx_fifo_g_align;
bool man_start_com_g;
+ uint32_t dma_burst_size;
+ uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
} XlnxZynqMPQSPIPS;
typedef struct XilinxSPIPSClass {
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index bd6c1a7f96..040a088734 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -24,6 +24,8 @@
#include "qemu/timer.h"
+typedef struct AspeedSCUState AspeedSCUState;
+
#define ASPEED_TIMER(obj) \
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
#define TYPE_ASPEED_TIMER "aspeed.timer"
@@ -55,6 +57,8 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
+
+ AspeedSCUState *scu;
} AspeedTimerCtrlState;
#endif /* ASPEED_TIMER_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 04:33:02 +0000