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Diffstat (limited to 'hw/m48t59.c')
-rw-r--r--hw/m48t59.c67
1 files changed, 33 insertions, 34 deletions
diff --git a/hw/m48t59.c b/hw/m48t59.c
index ce38f8b6ec..c3d7b3a256 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -49,7 +49,7 @@
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
*/
-struct m48t59_t {
+struct M48t59State {
/* Model parameters */
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
@@ -71,12 +71,12 @@ struct m48t59_t {
typedef struct M48t59ISAState {
ISADevice busdev;
- m48t59_t state;
+ M48t59State state;
} M48t59ISAState;
typedef struct M48t59SysBusState {
SysBusDevice busdev;
- m48t59_t state;
+ M48t59State state;
} M48t59SysBusState;
/* Fake timer functions */
@@ -86,7 +86,7 @@ static void alarm_cb (void *opaque)
{
struct tm tm;
uint64_t next_time;
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
@@ -128,7 +128,7 @@ static void alarm_cb (void *opaque)
qemu_set_irq(NVRAM->IRQ, 0);
}
-static void set_alarm (m48t59_t *NVRAM)
+static void set_alarm(M48t59State *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
@@ -140,12 +140,12 @@ static void set_alarm (m48t59_t *NVRAM)
}
/* RTC management helpers */
-static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
+static inline void get_time(M48t59State *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
-static void set_time (m48t59_t *NVRAM, struct tm *tm)
+static void set_time(M48t59State *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
@@ -154,7 +154,7 @@ static void set_time (m48t59_t *NVRAM, struct tm *tm)
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
@@ -168,7 +168,7 @@ static void watchdog_cb (void *opaque)
}
}
-static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
+static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
@@ -186,7 +186,7 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
int tmp;
@@ -354,7 +354,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
@@ -461,14 +461,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
void m48t59_set_addr (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
@@ -476,7 +476,7 @@ void m48t59_toggle_lock (void *opaque, int lock)
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
@@ -500,7 +500,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
@@ -519,14 +519,14 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
@@ -534,7 +534,7 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@@ -544,7 +544,7 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
@@ -553,7 +553,7 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
@@ -563,7 +563,7 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
@@ -587,7 +587,7 @@ static CPUReadMemoryFunc * const nvram_read[] = {
static void m48t59_save(QEMUFile *f, void *opaque)
{
- m48t59_t *s = opaque;
+ M48t59State *s = opaque;
qemu_put_8s(f, &s->lock);
qemu_put_be16s(f, &s->addr);
@@ -596,7 +596,7 @@ static void m48t59_save(QEMUFile *f, void *opaque)
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
- m48t59_t *s = opaque;
+ M48t59State *s = opaque;
if (version_id != 1)
return -EINVAL;
@@ -608,7 +608,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-static void m48t59_reset_common(m48t59_t *NVRAM)
+static void m48t59_reset_common(M48t59State *NVRAM)
{
NVRAM->addr = 0;
NVRAM->lock = 0;
@@ -622,7 +622,7 @@ static void m48t59_reset_common(m48t59_t *NVRAM)
static void m48t59_reset_isa(DeviceState *d)
{
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
- m48t59_t *NVRAM = &isa->state;
+ M48t59State *NVRAM = &isa->state;
m48t59_reset_common(NVRAM);
}
@@ -630,15 +630,14 @@ static void m48t59_reset_isa(DeviceState *d)
static void m48t59_reset_sysbus(DeviceState *d)
{
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
- m48t59_t *NVRAM = &sys->state;
+ M48t59State *NVRAM = &sys->state;
m48t59_reset_common(NVRAM);
}
/* Initialisation routine */
-m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size,
- int type)
+M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+ uint32_t io_base, uint16_t size, int type)
{
DeviceState *dev;
SysBusDevice *s;
@@ -664,11 +663,11 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
return &d->state;
}
-m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
+M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
M48t59ISAState *d;
ISADevice *dev;
- m48t59_t *s;
+ M48t59State *s;
dev = isa_create("m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type);
@@ -686,7 +685,7 @@ m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
return s;
}
-static void m48t59_init_common(m48t59_t *s)
+static void m48t59_init_common(M48t59State *s)
{
s->buffer = qemu_mallocz(s->size);
if (s->type == 59) {
@@ -701,7 +700,7 @@ static void m48t59_init_common(m48t59_t *s)
static int m48t59_init_isa1(ISADevice *dev)
{
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
- m48t59_t *s = &d->state;
+ M48t59State *s = &d->state;
isa_init_irq(dev, &s->IRQ, 8);
m48t59_init_common(s);
@@ -712,7 +711,7 @@ static int m48t59_init_isa1(ISADevice *dev)
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
- m48t59_t *s = &d->state;
+ M48t59State *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 05:57:17 +0000