diff options
| -rw-r--r-- | target/ppc/fpu_helper.c | 6 | ||||
| -rw-r--r-- | target/ppc/helper.h | 8 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 24 |
3 files changed, 26 insertions, 12 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 902d63b139..5fb43b619e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2236,9 +2236,8 @@ VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23) * nbits - number of fraction bits */ #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xb = &env->vsr[xB(opcode)]; \ int i; \ int fe_flag = 0; \ int fg_flag = 0; \ @@ -3258,9 +3257,8 @@ VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0) VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1) VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1) -void helper_xststdcsp(CPUPPCState *env, uint32_t opcode) +void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) { - ppc_vsr_t *xb = &env->vsr[xB(opcode)]; uint32_t dcmx, sign, exp; uint32_t cc, match = 0, not_sp = 0; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 0ab1ef2aee..a8886c56ad 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -376,7 +376,7 @@ DEF_HELPER_3(xsredp, void, env, vsr, vsr) DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xstsqrtdp, void, env, i32) +DEF_HELPER_3(xstsqrtdp, void, env, i32, vsr) DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmsubadp, void, env, vsr, vsr, vsr) @@ -423,7 +423,7 @@ DEF_HELPER_3(xscvuxdsp, void, env, vsr, vsr) DEF_HELPER_3(xscvsxdsp, void, env, vsr, vsr) DEF_HELPER_2(xscvudqp, void, env, i32) DEF_HELPER_3(xscvuxddp, void, env, vsr, vsr) -DEF_HELPER_2(xststdcsp, void, env, i32) +DEF_HELPER_3(xststdcsp, void, env, i32, vsr) DEF_HELPER_2(xststdcdp, void, env, i32) DEF_HELPER_2(xststdcqp, void, env, i32) DEF_HELPER_3(xsrdpi, void, env, vsr, vsr) @@ -461,7 +461,7 @@ DEF_HELPER_3(xvredp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xvtsqrtdp, void, env, i32) +DEF_HELPER_3(xvtsqrtdp, void, env, i32, vsr) DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmsubadp, void, env, vsr, vsr, vsr) @@ -499,7 +499,7 @@ DEF_HELPER_3(xvresp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivsp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xvtsqrtsp, void, env, i32) +DEF_HELPER_3(xvtsqrtsp, void, env, i32, vsr) DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmsubasp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 9b4603ac33..8af093d256 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1079,6 +1079,22 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_ptr(xb); \ } +#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + gen_helper_##name(cpu_env, opc, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xb); \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1108,7 +1124,7 @@ GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) @@ -1181,7 +1197,7 @@ GEN_VSX_HELPER_X3(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) @@ -1193,7 +1209,7 @@ GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) @@ -1227,7 +1243,7 @@ GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) |