diff options
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 22 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-ops.inc.c | 1 |
2 files changed, 23 insertions, 0 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 2d09225c84..ed392aaea1 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1263,6 +1263,28 @@ static void gen_xsiexpdp(DisasContext *ctx) tcg_temp_free_i64(t0); } +static void gen_xsiexpqp(DisasContext *ctx) +{ + TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); + TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32); + TCGv_i64 xah = cpu_vsrh(rA(ctx->opcode) + 32); + TCGv_i64 xal = cpu_vsrl(rA(ctx->opcode) + 32); + TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32); + TCGv_i64 t0; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF); + tcg_gen_andi_i64(t0, xbh, 0x7FFF); + tcg_gen_shli_i64(t0, t0, 48); + tcg_gen_or_i64(xth, xth, t0); + tcg_gen_mov_i64(xtl, xal); + tcg_temp_free_i64(t0); +} + static void gen_xsxsigdp(DisasContext *ctx) { TCGv rt = cpu_gpr[rD(ctx->opcode)]; diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index 5980ac6e72..09b91c389f 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -121,6 +121,7 @@ GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001), GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300), GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001), GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300), +GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001), #endif GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |