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-rw-r--r--target-arm/Makefile.objs2
-rw-r--r--target-arm/cpu-qom.h5
-rw-r--r--target-arm/cpu64.c3
-rw-r--r--target-arm/translate-a64.c139
-rw-r--r--target-arm/translate.c14
-rw-r--r--target-arm/translate.h19
6 files changed, 178 insertions, 4 deletions
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index baebc50f68..a11d76ee57 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -5,4 +5,4 @@ obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += neon_helper.o iwmmxt_helper.o
obj-y += gdbstub.o
-obj-$(TARGET_AARCH64) += cpu64.o
+obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index fbe846e373..6502a7b7b3 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -173,4 +173,9 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
+#ifdef TARGET_AARCH64
+void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
+#endif
+
#endif
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index faee0f048f..4428f6cffd 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -70,6 +70,9 @@ static void aarch64_cpu_finalizefn(Object *obj)
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
+
+ cc->dump_state = aarch64_cpu_dump_state;
}
static void aarch64_cpu_register(const ARMCPUInfo *info)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
new file mode 100644
index 0000000000..f120088607
--- /dev/null
+++ b/target-arm/translate-a64.c
@@ -0,0 +1,139 @@
+/*
+ * AArch64 translation
+ *
+ * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "cpu.h"
+#include "tcg-op.h"
+#include "qemu/log.h"
+#include "translate.h"
+#include "qemu/host-utils.h"
+
+#include "helper.h"
+#define GEN_HELPER 1
+#include "helper.h"
+
+static TCGv_i64 cpu_X[32];
+static TCGv_i64 cpu_pc;
+static TCGv_i32 pstate;
+
+static const char *regnames[] = {
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
+};
+
+/* initialize TCG globals. */
+void a64_translate_init(void)
+{
+ int i;
+
+ cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUARMState, pc),
+ "pc");
+ for (i = 0; i < 32; i++) {
+ cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUARMState, xregs[i]),
+ regnames[i]);
+ }
+
+ pstate = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUARMState, pstate),
+ "pstate");
+}
+
+void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ int i;
+
+ cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
+ env->pc, env->xregs[31]);
+ for (i = 0; i < 31; i++) {
+ cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
+ if ((i % 4) == 3) {
+ cpu_fprintf(f, "\n");
+ } else {
+ cpu_fprintf(f, " ");
+ }
+ }
+ cpu_fprintf(f, "PSTATE=%c%c%c%c\n",
+ env->pstate & PSTATE_N ? 'n' : '.',
+ env->pstate & PSTATE_Z ? 'z' : '.',
+ env->pstate & PSTATE_C ? 'c' : '.',
+ env->pstate & PSTATE_V ? 'v' : '.');
+ cpu_fprintf(f, "\n");
+}
+
+void gen_a64_set_pc_im(uint64_t val)
+{
+ tcg_gen_movi_i64(cpu_pc, val);
+}
+
+static void gen_exception(int excp)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(tmp, excp);
+ gen_helper_exception(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
+}
+
+static void gen_exception_insn(DisasContext *s, int offset, int excp)
+{
+ gen_a64_set_pc_im(s->pc - offset);
+ gen_exception(excp);
+ s->is_jmp = DISAS_JUMP;
+}
+
+static void real_unallocated_encoding(DisasContext *s)
+{
+ fprintf(stderr, "Unknown instruction: %#x\n", s->insn);
+ gen_exception_insn(s, 4, EXCP_UDEF);
+}
+
+#define unallocated_encoding(s) do { \
+ fprintf(stderr, "unallocated encoding at line: %d\n", __LINE__); \
+ real_unallocated_encoding(s); \
+ } while (0)
+
+void disas_a64_insn(CPUARMState *env, DisasContext *s)
+{
+ uint32_t insn;
+
+ insn = arm_ldl_code(env, s->pc, s->bswap_code);
+ s->insn = insn;
+ s->pc += 4;
+
+ switch ((insn >> 24) & 0x1f) {
+ default:
+ unallocated_encoding(s);
+ break;
+ }
+
+ if (unlikely(s->singlestep_enabled) && (s->is_jmp == DISAS_TB_JUMP)) {
+ /* go through the main loop for single step */
+ s->is_jmp = DISAS_JUMP;
+ }
+}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index db7a1d4dd5..998bde268d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -114,6 +114,8 @@ void arm_translate_init(void)
offsetof(CPUARMState, exclusive_info), "exclusive_info");
#endif
+ a64_translate_init();
+
#define GEN_HELPER 2
#include "helper.h"
}
@@ -907,7 +909,11 @@ DO_GEN_ST(st32)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
- tcg_gen_movi_i32(cpu_R[15], val);
+ if (s->aarch64) {
+ gen_a64_set_pc_im(val);
+ } else {
+ tcg_gen_movi_i32(cpu_R[15], val);
+ }
}
/* Force a TB lookup after an instruction that changes the CPU state. */
@@ -10099,7 +10105,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
do {
#ifdef CONFIG_USER_ONLY
/* Intercept jump to the magic kernel page. */
- if (dc->pc >= 0xffff0000) {
+ if (!dc->aarch64 && dc->pc >= 0xffff0000) {
/* We always get here via a jump, so know we are not in a
conditional execution block. */
gen_exception(EXCP_KERNEL_TRAP);
@@ -10147,7 +10153,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
tcg_gen_debug_insn_start(dc->pc);
}
- if (dc->thumb) {
+ if (dc->aarch64) {
+ disas_a64_insn(env, dc);
+ } else if (dc->thumb) {
disas_thumb_insn(env, dc);
if (dc->condexec_mask) {
dc->condexec_cond = (dc->condexec_cond & 0xe)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 5be2eedc90..67c776053b 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -4,6 +4,7 @@
/* internal defines */
typedef struct DisasContext {
target_ulong pc;
+ uint32_t insn;
int is_jmp;
/* Nonzero if this instruction has been conditionally skipped. */
int condjmp;
@@ -27,4 +28,22 @@ typedef struct DisasContext {
extern TCGv_ptr cpu_env;
+#ifdef TARGET_AARCH64
+void a64_translate_init(void);
+void disas_a64_insn(CPUARMState *env, DisasContext *s);
+void gen_a64_set_pc_im(uint64_t val);
+#else
+static inline void a64_translate_init(void)
+{
+}
+
+static inline void disas_a64_insn(CPUARMState *env, DisasContext *s)
+{
+}
+
+static inline void gen_a64_set_pc_im(uint64_t val)
+{
+}
+#endif
+
#endif /* TARGET_ARM_TRANSLATE_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:55:33 +0000