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authorPeter Maydell <peter.maydell@linaro.org>2020-02-07 18:02:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-07 18:02:52 +0000
commit93c86fff53a267f657e79ec07dcd04b63882e330 (patch)
treeac42b0e25fcbcb1aa437d5171f7148199c11dee7 /tests/qemu-iotests/218
parent42ccca1bd9456568f996d5646b2001faac96944b (diff)
parentaf6c91b490e9b1bce7a168f8a9c848f3e60f616e (diff)
downloadqemu-93c86fff53a267f657e79ec07dcd04b63882e330.zip
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200207' into staging
target-arm queue: * monitor: fix query-cpu-model-expansion crash when using machine type none * Support emulation of the ARMv8.1-VHE architecture feature * bcm2835_dma: fix bugs in TD mode handling * docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer * stellaris, stm32f2xx_timer, armv7m_systick: fix minor memory leaks # gpg: Signature made Fri 07 Feb 2020 14:32:28 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200207: (48 commits) stellaris: delay timer_new to avoid memleaks stm32f2xx_timer: delay timer_new to avoid memleaks armv7m_systick: delay timer_new to avoid memleaks docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer bcm2835_dma: Re-initialize xlen in TD mode bcm2835_dma: Fix the ylen loop in TD mode target/arm: Raise only one interrupt in arm_cpu_exec_interrupt target/arm: Use bool for unmasked in arm_excp_unmasked target/arm: Pass more cpu state to arm_excp_unmasked target/arm: Move arm_excp_unmasked to cpu.c target/arm: Enable ARMv8.1-VHE in -cpu max target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE target/arm: Update get_a64_user_mem_index for VHE target/arm: check TGE and E2H flags for EL0 pauth traps target/arm: Update {fp,sve}_exception_el for VHE target/arm: Update arm_phys_excp_target_el for TGE target/arm: Flush tlbs for E2&0 translation regime target/arm: Flush tlb for ASID changes in EL2&0 translation regime target/arm: Add VHE timer register redirection and aliasing target/arm: Add VHE system register redirection and aliasing ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/qemu-iotests/218')
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