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| author | Richard Henderson <rth@twiddle.net> | 2016-07-14 12:43:06 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-09-16 08:12:06 -0700 |
| commit | 85aa80813dd9f5c1f581c743e45678a3bee220f8 (patch) | |
| tree | 2a140ecb81d60cf1a593a160c0d09f88ae5a3c7d /tcg/s390 | |
| parent | ebc231d7daf1f41b23d8b6a6d1234800b86e5fe2 (diff) | |
| download | qemu-85aa80813dd9f5c1f581c743e45678a3bee220f8.zip | |
tcg: Support arbitrary size + alignment
Previously we allowed fully unaligned operations, but not operations
that are aligned but with less alignment than the operation size.
In addition, arm32, ia64, mips, and sparc had been omitted from the
previous overalignment patch, which would have led to that alignment
being enforced.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/s390')
| -rw-r--r-- | tcg/s390/tcg-target.inc.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5a7495b063..f0c88de6d3 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1505,21 +1505,18 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc, int mem_index, bool is_ld) { - int a_bits = get_alignment_bits(opc); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + unsigned s_mask = (1 << s_bits) - 1; + unsigned a_mask = (1 << a_bits) - 1; int ofs, a_off; uint64_t tlb_mask; /* For aligned accesses, we check the first byte and include the alignment bits within the address. For unaligned access, we check that we don't cross pages using the address of the last byte of the access. */ - if (a_bits >= 0) { - /* A byte access or an alignment check required */ - a_off = 0; - tlb_mask = TARGET_PAGE_MASK | ((1 << a_bits) - 1); - } else { - a_off = (1 << (opc & MO_SIZE)) - 1; - tlb_mask = TARGET_PAGE_MASK; - } + a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); + tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; if (facilities & FACILITY_GEN_INST_EXT) { tcg_out_risbg(s, TCG_REG_R2, addr_reg, |