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| author | Richard Henderson <rth@twiddle.net> | 2015-07-24 07:16:00 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-08-24 11:10:54 -0700 |
| commit | 609ad70562793937257c89d07bf7c1370b9fc9aa (patch) | |
| tree | fd10a7febb6cfe6934d301b2b2dc7b675bade774 /tcg/i386/tcg-target.h | |
| parent | 870ad1547ac53bc79c21d86cf453b3b20cc660a2 (diff) | |
| download | qemu-609ad70562793937257c89d07bf7c1370b9fc9aa.zip | |
tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32
Rather than allow arbitrary shift+trunc, only concern ourselves
with low and high parts. This is all that was being used anyway.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/i386/tcg-target.h')
| -rw-r--r-- | tcg/i386/tcg-target.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index dae50ba368..92be341713 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -102,7 +102,8 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_mulsh_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_trunc_shr_i64_i32 0 +#define TCG_TARGET_HAS_extrl_i64_i32 0 +#define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 |