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authorSebastian Andrzej Siewior <bigeasy@linutronix.de>2019-09-25 23:49:48 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2019-10-04 18:49:17 +0200
commite900135dcfb676a4019dc206395e02db5d1de0d6 (patch)
tree11eac751d1c9824e49c0ede3034e5c95ade8153a /target
parent6f89ec7442ef4a7c7a826ab0809c5583f75de4bf (diff)
downloadqemu-e900135dcfb676a4019dc206395e02db5d1de0d6.zip
i386: Add CPUID bit for CLZERO and XSAVEERPTR
The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform and could be passed to the guest. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/i386/cpu.c2
-rw-r--r--target/i386/cpu.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9e0bac31e8..2b7225f875 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1134,7 +1134,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_8000_0008_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- NULL, NULL, NULL, NULL,
+ "clzero", NULL, "xsaveerptr", NULL,
NULL, NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL,
"ibpb", NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5f6e3a029a..87f4afbfd6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -695,6 +695,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
+#define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */
+#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
do not invalidate cache */
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */