diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-07-03 08:17:26 -0700 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-08-21 14:28:45 +1000 |
| commit | e82c42b7c5c1acbcfd5e5fe2b1b850c56e619c0d (patch) | |
| tree | 443402216f196353a9fc3ce4e698a6382b586abb /target | |
| parent | 1368898d4b7e36f8a69e4dfd017853e15de6ef81 (diff) | |
| download | qemu-e82c42b7c5c1acbcfd5e5fe2b1b850c56e619c0d.zip | |
target/ppc: Enable fp exceptions for user-only
While just setting the MSR bits is sufficient, we can tidy
the helper code by extracting the MSR test to a helper and
then forcing it true for user-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/fpu_helper.c | 15 | ||||
| -rw-r--r-- | target/ppc/translate_init.inc.c | 2 |
2 files changed, 14 insertions, 3 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8675d931b6..9b39c4b3e5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -36,6 +36,15 @@ static inline float128 float128_snan_to_qnan(float128 x) #define float32_snan_to_qnan(x) ((x) | 0x00400000) #define float16_snan_to_qnan(x) ((x) | 0x0200) +static inline bool fp_exceptions_enabled(CPUPPCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0; +#endif +} + /*****************************************************************************/ /* Floating point operations helpers */ uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) @@ -207,7 +216,7 @@ uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) if (ve != 0) { /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { /* GETPC() works here because this is inline */ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op, GETPC()); @@ -225,7 +234,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr) if (fpscr_ze != 0) { /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX, raddr); @@ -555,7 +564,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { raise_exception_err_ra(env, cs->exception_index, env->error_code, raddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 7813b1b004..fe0cb98e6d 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10278,6 +10278,8 @@ static void ppc_cpu_reset(CPUState *s) #endif #if defined(CONFIG_USER_ONLY) msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ + msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ + msr |= (target_ulong)1 << MSR_FE1; msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |