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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-03-09 11:22:18 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-09 11:22:18 +0000 |
| commit | bb5643ff61291deb1d198f343a03828c5ead993f (patch) | |
| tree | 6cfb82e21113b7a7f6a3b9a03a0c0789ade903b2 /target | |
| parent | 74fd46ed44f60a230804dc1050bae76eb9420ecb (diff) | |
| parent | 2526e69efd8e386573212bf3ea05171a727a598b (diff) | |
| download | qemu-bb5643ff61291deb1d198f343a03828c5ead993f.zip | |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210306' into staging
Add hexagon to include/exec/poison.h
Two Coverity fixes for target/hexagon/
# gpg: Signature made Sun 07 Mar 2021 01:37:05 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-hex-20210306:
target/hexagon/opcodes: Add missing varargs cleanup
target/hexagon: Fix shift amount check in fASHIFTL/fLSHIFTR
exec: Poison Hexagon target-specific definitions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/hexagon/macros.h | 4 | ||||
| -rw-r--r-- | target/hexagon/opcodes.c | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 78c4efb5cb..cfcb8173ba 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -459,7 +459,7 @@ static inline void gen_logical_not(TCGv dest, TCGv src) : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ - (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) + (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) #define fROTL(SRC, SHAMT, REGSTYPE) \ (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ ((fCAST##REGSTYPE##u(SRC) >> \ @@ -469,7 +469,7 @@ static inline void gen_logical_not(TCGv dest, TCGv src) ((fCAST##REGSTYPE##u(SRC) << \ ((sizeof(SRC) * 8) - (SHAMT)))))) #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ - (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) + (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) #ifdef QEMU_GENERATE #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) diff --git a/target/hexagon/opcodes.c b/target/hexagon/opcodes.c index 4eef5fc40f..35d790cdd5 100644 --- a/target/hexagon/opcodes.c +++ b/target/hexagon/opcodes.c @@ -82,6 +82,7 @@ static void init_attribs(int tag, ...) while ((attr = va_arg(ap, int)) != 0) { set_bit(attr, opcode_attribs[tag]); } + va_end(ap); } const OpcodeEncoding opcode_encodings[] = { |