diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-04-19 13:22:39 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-30 11:16:50 +0100 |
| commit | 9565ac4cc7e1d1aaccf3d8c6aed423b776e7995f (patch) | |
| tree | f6d97f267f5a51dea6961bc4b793967e55b506a3 /target | |
| parent | 37bf7a055f6b26a398dd0e953bf73d44e2312b33 (diff) | |
| download | qemu-9565ac4cc7e1d1aaccf3d8c6aed423b776e7995f.zip | |
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f2a6d76b4..e99c0ab5cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, tcg_gen_qemu_ld_i64(val, addr, index, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { tcg_gen_rotri_i64(val, val, 32); } @@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, TCGv addr = gen_aa32_addr(s, a32, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_rotri_i64(tmp, val, 32); tcg_gen_qemu_st_i64(tmp, addr, index, opc); |