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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-02-13 13:40:59 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-13 13:40:59 +0000 |
| commit | 81f49abaaac2b88062bd1b07f451d9527ed1c9ce (patch) | |
| tree | fcfbe2c6aaad9ea3d4dffd941567f2a48e6f14f6 /target | |
| parent | 7ce9ce89930ce260af839fb3e3e5f9101f5c69a0 (diff) | |
| parent | be02cda3afde60d219786e23c3f8edb53aec8e17 (diff) | |
| download | qemu-81f49abaaac2b88062bd1b07f451d9527ed1c9ce.zip | |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* various small fixes and cleanups
* fixes for the ucode revision patch from the previous pull request
# gpg: Signature made Wed 12 Feb 2020 15:30:24 GMT
# gpg: using RSA key BFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream:
target/i386: enable monitor and ucode revision with -cpu max
target/i386: check for availability of MSR_IA32_UCODE_REV as an emulated MSR
target/i386: fix TCG UCODE_REV access
build: move TARGET_GPROF to config-host.mak
exec: do not define use_icount for user-mode emulation
minikconf: accept alnum identifiers
Remove support for CLOCK_MONOTONIC not being defined
seqlock: fix seqlock_write_unlock_impl function
vl: Don't mismatch g_strsplit()/g_free()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/kvm.c | 7 | ||||
| -rw-r--r-- | target/i386/misc_helper.c | 8 |
3 files changed, 11 insertions, 6 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 32efa46852..92fafa2659 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6414,7 +6414,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) error_setg(&local_err, "CPU model '%s' requires KVM", name); goto out; } + } + if (cpu->max_features && accel_uses_host_cpuid()) { if (enable_cpu_pm) { host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, &cpu->mwait.ecx, &cpu->mwait.edx); diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6ef291d580..69eb43d796 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -105,6 +105,7 @@ static bool has_msr_smi_count; static bool has_msr_arch_capabs; static bool has_msr_core_capabs; static bool has_msr_vmx_vmfunc; +static bool has_msr_ucode_rev; static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -2056,6 +2057,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_VMX_VMFUNC: has_msr_vmx_vmfunc = true; break; + case MSR_IA32_UCODE_REV: + has_msr_ucode_rev = true; + break; } } } @@ -2696,8 +2700,7 @@ static void kvm_init_msrs(X86CPU *cpu) env->features[FEAT_CORE_CAPABILITY]); } - if (kvm_arch_get_supported_msr_feature(kvm_state, - MSR_IA32_UCODE_REV)) { + if (has_msr_ucode_rev) { kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); } diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index aed16fe3f0..7d61221024 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -229,7 +229,6 @@ void helper_rdmsr(CPUX86State *env) #else void helper_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); uint64_t val; cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); @@ -372,9 +371,6 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; - case MSR_IA32_UCODE_REV: - val = x86_cpu->ucode_rev; - break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + @@ -393,6 +389,7 @@ void helper_wrmsr(CPUX86State *env) void helper_rdmsr(CPUX86State *env) { + X86CPU *x86_cpu = env_archcpu(env); uint64_t val; cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC()); @@ -526,6 +523,9 @@ void helper_rdmsr(CPUX86State *env) case MSR_IA32_BNDCFGS: val = env->msr_bndcfgs; break; + case MSR_IA32_UCODE_REV: + val = x86_cpu->ucode_rev; + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + |