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author | Peter Maydell <peter.maydell@linaro.org> | 2021-05-27 19:17:42 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-27 19:17:42 +0100 |
commit | 7258034ab40e6927acbd005feb295eb3acf972bb (patch) | |
tree | 2f30a06432f7049429f41ccea808c5f683a94eba /target | |
parent | c8616fc7670b884de5f74d2767aade224c1c5c3a (diff) | |
parent | 5e50c6c72bf8575f124ec9397411f4a2ff0d0206 (diff) | |
download | qemu-7258034ab40e6927acbd005feb295eb3acf972bb.zip |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.1-pull-request' into staging
m68k pull request 20210526
implement m68k "any instruction" trace mode
# gpg: Signature made Wed 26 May 2021 20:56:58 BST
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-6.1-pull-request:
target/m68k: implement m68k "any instruction" trace mode
target/m68k: introduce gen_singlestep_exception() function
target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb()
target/m68k: introduce is_singlestepping() function
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/m68k/cpu.h | 8 | ||||
-rw-r--r-- | target/m68k/translate.c | 51 |
2 files changed, 51 insertions, 8 deletions
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 402c86c876..997d588911 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -230,6 +230,9 @@ typedef enum { #define SR_T_SHIFT 14 #define SR_T 0xc000 +#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) +#define M68K_SR_TRACE_ANY_INS 0x2 + #define M68K_SSP 0 #define M68K_USP 1 #define M68K_ISP 2 @@ -590,6 +593,8 @@ typedef M68kCPU ArchCPU; #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) #define TB_FLAGS_DFC_S_BIT 15 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) +#define TB_FLAGS_TRACE 16 +#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -602,6 +607,9 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } + if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { + *flags |= TB_FLAGS_TRACE; + } } void dump_mmu(CPUM68KState *env); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 200018ae6a..f0c5bf9154 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -124,6 +124,7 @@ typedef struct DisasContext { #define MAX_TO_RELEASE 8 int release_count; TCGv release[MAX_TO_RELEASE]; + bool ss_active; } DisasContext; static void init_release_array(DisasContext *s) @@ -194,6 +195,18 @@ static void do_writebacks(DisasContext *s) } } +static bool is_singlestepping(DisasContext *s) +{ + /* + * Return true if we are singlestepping either because of + * architectural singlestep or QEMU gdbstub singlestep. This does + * not include the command line '-singlestep' mode which is rather + * misnamed as it only means "one instruction per TB" and doesn't + * affect the code we generate. + */ + return s->base.singlestep_enabled || s->ss_active; +} + /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */ @@ -308,6 +321,20 @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr) s->base.is_jmp = DISAS_NORETURN; } +static void gen_singlestep_exception(DisasContext *s) +{ + /* + * Generate the right kind of exception for singlestep, which is + * either the architectural singlestep or EXCP_DEBUG for QEMU's + * gdb singlestepping. + */ + if (s->ss_active) { + gen_raise_exception(EXCP_TRACE); + } else { + gen_raise_exception(EXCP_DEBUG); + } +} + static inline void gen_addr_fault(DisasContext *s) { gen_exception(s, s->base.pc_next, EXCP_ADDRESS); @@ -1506,8 +1533,10 @@ static inline bool use_goto_tb(DisasContext *s, uint32_t dest) /* Generate a jump to an immediate address. */ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) { - if (unlikely(s->base.singlestep_enabled)) { - gen_exception(s, dest, EXCP_DEBUG); + if (unlikely(is_singlestepping(s))) { + update_cc_op(s); + tcg_gen_movi_i32(QREG_PC, dest); + gen_singlestep_exception(s); } else if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(QREG_PC, dest); @@ -6172,6 +6201,12 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->done_mac = 0; dc->writeback_mask = 0; init_release_array(dc); + + dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS); + /* If architectural single step active, limit to 1 */ + if (is_singlestepping(dc)) { + dc->base.max_insns = 1; + } } static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) @@ -6245,17 +6280,17 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; case DISAS_TOO_MANY: update_cc_op(dc); - if (dc->base.singlestep_enabled) { + if (is_singlestepping(dc)) { tcg_gen_movi_i32(QREG_PC, dc->pc); - gen_raise_exception(EXCP_DEBUG); + gen_singlestep_exception(dc); } else { gen_jmp_tb(dc, 0, dc->pc); } break; case DISAS_JUMP: /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */ - if (dc->base.singlestep_enabled) { - gen_raise_exception(EXCP_DEBUG); + if (is_singlestepping(dc)) { + gen_singlestep_exception(dc); } else { tcg_gen_lookup_and_goto_ptr(); } @@ -6265,8 +6300,8 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * We updated CC_OP and PC in gen_exit_tb, but also modified * other state that may require returning to the main loop. */ - if (dc->base.singlestep_enabled) { - gen_raise_exception(EXCP_DEBUG); + if (is_singlestepping(dc)) { + gen_singlestep_exception(dc); } else { tcg_gen_exit_tb(NULL, 0); } |