diff options
| author | Ilya Leoshkevich <iii@linux.ibm.com> | 2021-04-16 17:49:37 +0200 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2021-05-20 14:19:30 +0200 |
| commit | 48a130923c59b706e7f33527490028eb8a86b97e (patch) | |
| tree | 201ad2431068b68a02713cad19ebadce4cff35a2 /target | |
| parent | 86131c71b13257e095d8c4f4453d52cbc6553c07 (diff) | |
| download | qemu-48a130923c59b706e7f33527490028eb8a86b97e.zip | |
target/arm: Make sure that commpage's tb->size != 0
tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.
Fix by pretending that commpage translation blocks have at least one
instruction.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210416154939.32404-3-iii@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 455352bcf6..8e0e55c1e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8981,6 +8981,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) unsigned int insn; if (arm_pre_translate_insn(dc)) { + dc->base.pc_next += 4; return; } @@ -9050,6 +9051,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) bool is_16bit; if (arm_pre_translate_insn(dc)) { + dc->base.pc_next += 2; return; } |