diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:05 +0100 |
| commit | 43c4be1236c105090d134540da1036073d157cd4 (patch) | |
| tree | 79bad064c33a85ad39eaa8c01fa808125ab56147 /target | |
| parent | 88c5188ced60e9f2b8cc3af3b9bc4a8031c8c996 (diff) | |
| download | qemu-43c4be1236c105090d134540da1036073d157cd4.zip | |
target/arm: Convert VNMUL to decodetree
Convert the VNMUL instruction to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-vfp.inc.c | 24 | ||||
| -rw-r--r-- | target/arm/translate.c | 7 | ||||
| -rw-r--r-- | target/arm/vfp.decode | 5 |
3 files changed, 30 insertions, 6 deletions
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a2afe82b34..4c684f033b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1427,3 +1427,27 @@ static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_sp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false); } + +static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muls(vd, vn, vm, fpst); + gen_helper_vfp_negs(vd, vd); +} + +static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false); +} + +static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muld(vd, vn, vm, fpst); + gen_helper_vfp_negd(vd, vd); +} + +static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_sp *a) +{ + return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index a3e13c7c74..24c2425132 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1388,7 +1388,6 @@ static inline void gen_vfp_##name(int dp) \ VFP_OP2(add) VFP_OP2(sub) -VFP_OP2(mul) VFP_OP2(div) #undef VFP_OP2 @@ -3112,7 +3111,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) rn = VFP_SREG_N(insn); switch (op) { - case 0 ... 4: + case 0 ... 5: /* Already handled by decodetree */ return 1; default: @@ -3298,10 +3297,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 5: /* nmul: -(fn * fm) */ - gen_vfp_mul(dp); - gen_vfp_neg(dp); - break; case 6: /* add: fn + fm */ gen_vfp_add(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index d7fcb9709a..3063fcac23 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -122,3 +122,8 @@ VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ vm=%vm_sp vn=%vn_sp vd=%vd_sp VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp + +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ + vm=%vm_sp vn=%vn_sp vd=%vd_sp +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ + vm=%vm_dp vn=%vn_dp vd=%vd_dp |