diff options
| author | Frank Chang <frank.chang@sifive.com> | 2021-05-06 00:06:04 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:44 +1000 |
| commit | 1e16310ca1bd368f20eb93683cc37389d5db185d (patch) | |
| tree | 6a6e263669f9ec3f9b0ace22c23f5096f515e2dd /target | |
| parent | 438240185a9456747b19a29290018316271a3762 (diff) | |
| download | qemu-1e16310ca1bd368f20eb93683cc37389d5db185d.zip | |
target/riscv: rvb: count bits set
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn32.decode | 2 | ||||
| -rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 13 | ||||
| -rw-r--r-- | target/riscv/translate.c | 6 |
3 files changed, 21 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9a2ffab150..6f7671872d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -662,7 +662,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm # *** RV32B Standard Extension *** clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 +cpop 011000 000010 ..... 001 ..... 0010011 @r2 # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 157b4e3c41..4a5d271b43 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a) return gen_unary(ctx, a, gen_ctz); } +static bool trans_cpop(DisasContext *ctx, arg_cpop *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, tcg_gen_ctpop_tl); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -42,3 +48,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) REQUIRE_EXT(ctx, RVB); return gen_unary(ctx, a, gen_ctzw); } + +static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, gen_cpopw); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 60fac0fe27..c1a30c2172 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -561,6 +561,12 @@ static void gen_clzw(TCGv ret, TCGv arg1) tcg_gen_subi_tl(ret, ret, 32); } +static void gen_cpopw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_ctpop_tl(ret, arg1); +} + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { |