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| author | Max Filippov <jcmvbkbc@gmail.com> | 2011-11-26 15:48:41 +0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-16 19:19:03 -0800 |
| commit | 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (patch) | |
| tree | d64a088bd5188f6b19fe1fcd341283140f5fcc0e /target/xtensa/overlay_tool.h | |
| parent | 8b912ff033cbc2e58476dfdc00fa2b8529c9eb96 (diff) | |
| download | qemu-3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02.zip | |
target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/overlay_tool.h')
| -rw-r--r-- | target/xtensa/overlay_tool.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index bf36b5cdf6..38e9be9ff5 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -63,6 +63,10 @@ #define XCHAL_LOOP_BUFFER_SIZE 0 #endif +#ifndef XCHAL_HAVE_EXTERN_REGS +#define XCHAL_HAVE_EXTERN_REGS 0 +#endif + #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) #define XTENSA_OPTIONS ( \ @@ -115,7 +119,8 @@ XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ - XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID)) + XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \ + XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS)) #ifndef XCHAL_WINDOW_OF4_VECOFS #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 |