diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:38:56 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511 (patch) | |
| tree | a17a73c4cda6e40394841b74bd5edcb852e9fb3c /target/riscv | |
| parent | ab3d207fe89bc0c63739db19e177af49179aa457 (diff) | |
| download | qemu-9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511.zip | |
target/riscv: cpu: Add a new 'resetvec' property
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 1 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bcdce85c5e..f6aeecac15 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -529,6 +529,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3589ae6ea..0d1728a8cd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; |