diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-24 13:29:50 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | 5f10e6d8959cff77e79119bcc93d8d7806c28654 (patch) | |
| tree | f23dd3742794514d8006d4efc1b8bb8200a799b2 /target/riscv | |
| parent | 3820602f8059dfd4034d38bb727cdbc8759631db (diff) | |
| download | qemu-5f10e6d8959cff77e79119bcc93d8d7806c28654.zip | |
target/riscv: Remove the hardcoded SSTATUS_SD macro
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 6 | ||||
| -rw-r--r-- | target/riscv/csr.c | 9 |
2 files changed, 8 insertions, 7 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 24d89939a0..3a0e79e545 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -403,12 +403,6 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000ULL -#if defined(TARGET_RISCV32) -#define SSTATUS_SD SSTATUS32_SD -#elif defined(TARGET_RISCV64) -#define SSTATUS_SD SSTATUS64_SD -#endif - /* hstatus CSR bits */ #define HSTATUS_VSBE 0x00000020 #define HSTATUS_GVA 0x00000040 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 97ceff718f..41951a0a84 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -459,7 +459,7 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; @@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask = (sstatus_v1_10_mask); + + if (riscv_cpu_is_32bit(env)) { + mask |= SSTATUS32_SD; + } else { + mask |= SSTATUS64_SD; + } + *val = env->mstatus & mask; return RISCV_EXCP_NONE; } |