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| author | Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 2021-03-11 10:47:38 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-22 21:54:40 -0400 |
| commit | 9d5451e077cd84809bcdf460c39b5f4fec17fc79 (patch) | |
| tree | f35cb6358f9d048430957f77f99d880f944f2f2d /target/riscv/op_helper.c | |
| parent | c346749ee9d75fcb11bb816d0665ce174425d667 (diff) | |
| download | qemu-9d5451e077cd84809bcdf460c39b5f4fec17fc79.zip | |
target/riscv: Fix read and write accesses to vsip and vsie
The previous implementation was broken in many ways:
- Used mideleg instead of hideleg to mask accesses
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/op_helper.c')
0 files changed, 0 insertions, 0 deletions