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authorPalmer Dabbelt <palmer@sifive.com>2019-06-24 01:59:05 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-06-25 22:31:21 -0700
commit50fba816cd226001bec3e495c39879deb2fa5432 (patch)
tree0a8b056c8e90559d6a59fe53c53a8607617c08e4 /target/riscv/insn_trans
parent0a13a5b856ebb59dec6d165b87a0ba0e1e2dd952 (diff)
downloadqemu-50fba816cd226001bec3e495c39879deb2fa5432.zip
RISC-V: Add support for the Zifencei extension
fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
-rw-r--r--target/riscv/insn_trans/trans_rvi.inc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 6cda078ed6..ea6473111c 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -484,6 +484,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
{
+ if (!ctx->ext_ifencei) {
+ return false;
+ }
+
/*
* FENCE_I is a no-op in QEMU,
* however we need to end the translation block