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authorClaudio Fontana <cfontana@suse.de>2021-02-04 17:39:10 +0100
committerRichard Henderson <richard.henderson@linaro.org>2021-02-05 10:24:14 -1000
commit6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff (patch)
tree852544a19259ec1d208df3d7b33bf5891de1fda7 /target/riscv/cpu.c
parente9e51b7154404efc9af8735ab87c658a9c434cfd (diff)
downloadqemu-6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff.zip
target/riscv: remove CONFIG_TCG, as it is always TCG
for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-3-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/cpu.c')
-rw-r--r--target/riscv/cpu.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 567f6790a9..60d0b43153 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,10 +617,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-#ifdef CONFIG_TCG
cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
-#endif
+
device_class_set_props(dc, riscv_cpu_properties);
}