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authorPeter Maydell <peter.maydell@linaro.org>2019-01-09 16:08:31 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-01-09 16:08:31 +0000
commit8ae951fbc1068308313b2c57a4fc3c68451641f4 (patch)
tree0e6011b3ec47674859cd12a6e77ae8a8387f70a8 /target/ppc/translate_init.inc.c
parent147923b1a901a0370f83a0f4c58ec1baffef22f0 (diff)
parent3a8eb78e6c135422017888380db091793039b6dd (diff)
downloadqemu-8ae951fbc1068308313b2c57a4fc3c68451641f4.zip
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190109' into staging
ppc patch queue 2019-01-09 Second main pull request for qemu-4.0. Highlights are: * Final parts of XIVE support for pseries (without KVM) * Preliminary work for PHB hotplug * Starting to use TCG vector operations This includes some changes in the PCI core, which Michael Tsirkin requested come through this tree, since they're primarily of interest for ppc. # gpg: Signature made Tue 08 Jan 2019 22:44:10 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190109: (29 commits) spapr: enable XIVE MMIOs at reset spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS ppc/xics: allow ICSState to have an offset 0 spapr: move the qemu_irq array under the machine pnv/psi: move the ICSState qemu_irq array under the PSI device model ppc: export the XICS and XIVE set_irq handlers spapr: return from post_load method when RTC import fails ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU spapr: modify the prototype of the cpu_intc_create() method spapr/xive: simplify the sPAPR IRQ qirq method for XIVE spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h pci: allow cleanup/unregistration of PCI root buses spapr: move spapr_create_phb() to core machine code MAINTAINERS: add qemu_vga.ndrv file entry for Mac machines MAINTAINERS: Add some missing ppc-related files target/ppc: replace AVR* macros with Vsr* macros target/ppc: move FP and VMX registers into aligned vsr register array target/ppc: merge ppc_vsr_t and ppc_avr_t union types target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/ppc/translate_init.inc.c')
-rw-r--r--target/ppc/translate_init.inc.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 03f1d34a97..ade06cc773 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9486,7 +9486,7 @@ static bool avr_need_swap(CPUPPCState *env)
static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- stfq_p(mem_buf, env->fpr[n]);
+ stfq_p(mem_buf, *cpu_fpr_ptr(env, n));
ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
@@ -9502,7 +9502,7 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
ppc_maybe_bswap_register(env, mem_buf, 8);
- env->fpr[n] = ldfq_p(mem_buf);
+ *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
return 8;
}
if (n == 32) {
@@ -9516,12 +9516,13 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, n);
if (!avr_need_swap(env)) {
- stq_p(mem_buf, env->avr[n].u64[0]);
- stq_p(mem_buf+8, env->avr[n].u64[1]);
+ stq_p(mem_buf, avr->u64[0]);
+ stq_p(mem_buf + 8, avr->u64[1]);
} else {
- stq_p(mem_buf, env->avr[n].u64[1]);
- stq_p(mem_buf+8, env->avr[n].u64[0]);
+ stq_p(mem_buf, avr->u64[1]);
+ stq_p(mem_buf + 8, avr->u64[0]);
}
ppc_maybe_bswap_register(env, mem_buf, 8);
ppc_maybe_bswap_register(env, mem_buf + 8, 8);
@@ -9543,14 +9544,15 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, n);
ppc_maybe_bswap_register(env, mem_buf, 8);
ppc_maybe_bswap_register(env, mem_buf + 8, 8);
if (!avr_need_swap(env)) {
- env->avr[n].u64[0] = ldq_p(mem_buf);
- env->avr[n].u64[1] = ldq_p(mem_buf+8);
+ avr->u64[0] = ldq_p(mem_buf);
+ avr->u64[1] = ldq_p(mem_buf + 8);
} else {
- env->avr[n].u64[1] = ldq_p(mem_buf);
- env->avr[n].u64[0] = ldq_p(mem_buf+8);
+ avr->u64[1] = ldq_p(mem_buf);
+ avr->u64[0] = ldq_p(mem_buf + 8);
}
return 16;
}
@@ -9623,7 +9625,7 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- stq_p(mem_buf, env->vsr[n]);
+ stq_p(mem_buf, *cpu_vsrl_ptr(env, n));
ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
@@ -9634,7 +9636,7 @@ static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
ppc_maybe_bswap_register(env, mem_buf, 8);
- env->vsr[n] = ldq_p(mem_buf);
+ *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
return 8;
}
return 0;