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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:02:54 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:48:43 -0700 |
| commit | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 (patch) | |
| tree | 17c8eb391a8d03a3002cee3235df59bce50a7dd5 /target/ppc/translate | |
| parent | b72e3ff65880f2b894a2692e2b0a14424058a919 (diff) | |
| download | qemu-c7efab4fc1fe5092136305a2cae67fca03f4f9c5.zip | |
target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/ppc/translate')
0 files changed, 0 insertions, 0 deletions