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authorSuraj Jitindar Singh <sjitindarsingh@gmail.com>2017-05-02 16:37:16 +1000
committerDavid Gibson <david@gibson.dropbear.id.au>2017-05-11 09:45:15 +1000
commitc88305027d5a8dbeaacf04ad2ceba79a5c5fb91e (patch)
tree61d0e9fbcaa15662e1a1025c14b95b83cfe4972c /target/ppc/mmu-hash32.h
parentc6fd28fd573d69938e4da6ab3348b0695cad4f42 (diff)
downloadqemu-c88305027d5a8dbeaacf04ad2ceba79a5c5fb91e.zip
target/ppc: Change tlbie invalid fields for POWER9 support
The tlbie[l] instructions are used to invalidate TLB entries used to cache address translations. In ISAv3.00 (POWER9) more fields were added to the tblie[l] instructions which were previously invalid. We don't care about any of these new fields since we just invalidate the whole world anyway but we need to not cause an illegal instruction exception when the instructions are called. We also don't want to allow an older processor to have these fields set since that would be invalid. Add a new GEN_HANDLER for the ISAv3 instructions with the correct invalid mask. These will only be generated to a POWER9 processor for now based on the instruction flag. Also remove the PPC_MEM_TLBIE instruction flag from the POWER9 processor definition to ensure the old tlbie isn't generated. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/mmu-hash32.h')
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