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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-18 09:31:21 -0500 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-10-04 10:25:23 +1000 |
| commit | a2735cf483814b1c0e5773eee4a52f8e32d438cf (patch) | |
| tree | bd97e35550ae7cb6490901b2fbefdb9ce57dfbfa /target/ppc/internal.h | |
| parent | 4c3539d491026a0cc68e3b886f16cb7f57efd46b (diff) | |
| download | qemu-a2735cf483814b1c0e5773eee4a52f8e32d438cf.zip | |
ppc: Add support for 'mffscrn','mffscrni' instructions
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffscrn' and 'mffscrni' instructions.
'mffscrn' and 'mffscrni' are similar to 'mffsl', except they do not return
the status bits (FI, FR, FPRF) and they also set the rounding mode in the
FPSCR.
On CPUs without support for 'mffscrn'/'mffscrni' (below ISA 3.0), the
instructions will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Message-Id: <1568817081-1345-1-git-send-email-pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/internal.h')
| -rw-r--r-- | target/ppc/internal.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/ppc/internal.h b/target/ppc/internal.h index d3d327e548..15d655b356 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -157,6 +157,9 @@ EXTRACT_HELPER(FPL, 25, 1); EXTRACT_HELPER(FPFLM, 17, 8); EXTRACT_HELPER(FPW, 16, 1); +/* mffscrni */ +EXTRACT_HELPER(RM, 11, 2); + /* addpcis */ EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) #if defined(TARGET_PPC64) |