diff options
| author | Sandipan Das <sandipan@linux.vnet.ibm.com> | 2017-10-06 12:12:44 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-10-17 10:34:00 +1100 |
| commit | af1c259f6d4f1c6b0af22a0ff0b764c4ef3ef85e (patch) | |
| tree | c35aef8362fa07c002f014c4866070cf8c6bc2e7 /target/ppc/int_helper.c | |
| parent | 1ed9c8af501f8d1bdf5a8725a038527be059f54d (diff) | |
| download | qemu-af1c259f6d4f1c6b0af22a0ff0b764c4ef3ef85e.zip | |
target/ppc: Fix carry flag setting for shift algebraic instructions
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/int_helper.c')
| -rw-r--r-- | target/ppc/int_helper.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index da4e1a62c9..1c013a0ee3 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -219,17 +219,17 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulong value, shift &= 0x1f; ret = (int32_t)value >> shift; if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) { - env->ca = 0; + env->ca32 = env->ca = 0; } else { - env->ca = 1; + env->ca32 = env->ca = 1; } } else { ret = (int32_t)value; - env->ca = 0; + env->ca32 = env->ca = 0; } } else { ret = (int32_t)value >> 31; - env->ca = (ret != 0); + env->ca32 = env->ca = (ret != 0); } return (target_long)ret; } @@ -245,17 +245,17 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong value, shift &= 0x3f; ret = (int64_t)value >> shift; if (likely(ret >= 0 || (value & ((1ULL << shift) - 1)) == 0)) { - env->ca = 0; + env->ca32 = env->ca = 0; } else { - env->ca = 1; + env->ca32 = env->ca = 1; } } else { ret = (int64_t)value; - env->ca = 0; + env->ca32 = env->ca = 0; } } else { ret = (int64_t)value >> 63; - env->ca = (ret != 0); + env->ca32 = env->ca = (ret != 0); } return ret; } |