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authorRichard Henderson <richard.henderson@linaro.org>2018-02-20 10:28:01 -0800
committerRichard Henderson <richard.henderson@linaro.org>2018-05-14 14:54:24 -0700
commite720a5713dcfb7b2ea1d28c108353e7a12fea84d (patch)
treefed4bbc2e42ae07122fd4022ff61b6d467998b8d /target/openrisc/translate.c
parente20c2592bc6165bffeb968684e01bc26a6181a84 (diff)
downloadqemu-e720a5713dcfb7b2ea1d28c108353e7a12fea84d.zip
target/openrisc: Convert dec_M
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/translate.c')
-rw-r--r--target/openrisc/translate.c41
1 files changed, 13 insertions, 28 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index b5ff7577bd..bdd4626c02 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1030,32 +1030,21 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
return true;
}
-static void dec_M(DisasContext *dc, uint32_t insn)
+static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t rd;
- uint32_t K16;
- op0 = extract32(insn, 16, 1);
- rd = extract32(insn, 21, 5);
- K16 = extract32(insn, 0, 16);
-
- check_r0_write(rd);
- switch (op0) {
- case 0x0: /* l.movhi */
- LOG_DIS("l.movhi r%d, %d\n", rd, K16);
- tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
- break;
-
- case 0x1: /* l.macrc */
- LOG_DIS("l.macrc r%d\n", rd);
- tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac);
- tcg_gen_movi_i64(cpu_mac, 0);
- break;
+ LOG_DIS("l.movhi r%d, %d\n", a->d, a->k);
+ check_r0_write(a->d);
+ tcg_gen_movi_tl(cpu_R[a->d], a->k << 16);
+ return true;
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
+static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
+{
+ LOG_DIS("l.macrc r%d\n", a->d);
+ check_r0_write(a->d);
+ tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac);
+ tcg_gen_movi_i64(cpu_mac, 0);
+ return true;
}
static void dec_comp(DisasContext *dc, uint32_t insn)
@@ -1480,10 +1469,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
op0 = extract32(insn, 26, 6);
switch (op0) {
- case 0x06:
- dec_M(dc, insn);
- break;
-
case 0x2f:
dec_compi(dc, insn);
break;