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authorStafford Horne <shorne@gmail.com>2017-01-14 07:00:28 +0900
committerRichard Henderson <rth@twiddle.net>2017-02-14 08:14:59 +1100
commitc56e3b86701501364a4756201b6a9db9454463ab (patch)
tree2ec36a17efbf5e23b406ad00ca85e3f89b8ec941 /target/openrisc/mmu.c
parentc40413a65eeb98d6f9eeb92544ab782c812ccc51 (diff)
downloadqemu-c56e3b86701501364a4756201b6a9db9454463ab.zip
target/openrisc: Fix exception handling status registers
I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two issues by clearing the DSX flag when not in a delay slot and by setting EEAR to exception PC when handling illegal instruction exceptions. After this patch the openrisc kernel with latest patches boots great on qemu and instruction emulation works. Cc: qemu-trivial@nongnu.org Cc: openrisc@lists.librecores.org Signed-off-by: Stafford Horne <shorne@gmail.com> Message-Id: <20170113220028.29687-1-shorne@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/mmu.c')
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