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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 16:51:19 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | 23d45ebdb198378ae580c98ac898aa4b615059fd (patch) | |
| tree | 4463196c531f9677f1436f0c80132b1086642a19 /target/openrisc/machine.c | |
| parent | 455d45d22cc3b2c29c7840f2478647a0a3d9d8b4 (diff) | |
| download | qemu-23d45ebdb198378ae580c98ac898aa4b615059fd.zip | |
target/openrisc: Remove indirect function calls for mmu
There is no reason to use an indirect branch instead
of simply testing the SR bits that control mmu state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/machine.c')
| -rw-r--r-- | target/openrisc/machine.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env = opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry = { .name = "tlb_entry", .version_id = 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env = { .name = "env", .version_id = 6, .minimum_version_id = 6, - .post_load = env_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), |