diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-02 18:49:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-13 20:26:02 +0100 |
| commit | 17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3 (patch) | |
| tree | cd5bd83fc8738fae872942478003ac6baf5e7f4c /target/mips/cpu.h | |
| parent | 585c80ad7bb1bfd62721d03b62424fb1a786f659 (diff) | |
| download | qemu-17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3.zip | |
target/mips: Introduce ase_mt_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'Multi-Threading Present' bit, introduce an helper
to simplify code review.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5d3b2a01c0..3ac21d0e9c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ |