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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 22:33:37 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c (patch) | |
| tree | b493bacf05a8a4094393953193dfeba2a0510f1b /target/microblaze/op_helper.c | |
| parent | 0f96e96bd5144b1a834fed2b53a17fcf46637dcb (diff) | |
| download | qemu-3e0e16ae1e0048a21a91674061ec9c43c5d7a76c.zip | |
target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/op_helper.c')
| -rw-r--r-- | target/microblaze/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fdf706a723..a7f6cb71f1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; qemu_log("PC=%08x\n", env->pc); - qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); |