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| author | Laurent Vivier <laurent@vivier.eu> | 2018-01-18 20:38:42 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2018-01-25 16:02:24 +0100 |
| commit | c05c73b0838fc1b3fea87bc0ffa7b80b0556a2cb (patch) | |
| tree | 30cc7db72bc8ba443203e1ff5b46d4ca8ef86179 /target/m68k/cpu.h | |
| parent | 88b2fef6c3c3b45ac0dc2196ace7248a09c8e41d (diff) | |
| download | qemu-c05c73b0838fc1b3fea87bc0ffa7b80b0556a2cb.zip | |
target/m68k: add Transparent Translation
Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-4-laurent@vivier.eu>
Diffstat (limited to 'target/m68k/cpu.h')
| -rw-r--r-- | target/m68k/cpu.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 38a74476ee..1c2bbac56d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -76,6 +76,14 @@ #define EXCP_RTE 0x100 #define EXCP_HALT_INSN 0x101 +#define M68K_DTTR0 0 +#define M68K_DTTR1 1 +#define M68K_ITTR0 2 +#define M68K_ITTR1 3 + +#define M68K_MAX_TTR 2 +#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] + #define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 @@ -122,6 +130,7 @@ typedef struct CPUM68KState { uint32_t urp; uint32_t srp; bool fault; + uint32_t ttr[4]; } mmu; /* Control registers. */ @@ -318,6 +327,15 @@ typedef enum { #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) #define M68K_INDIRECT_POINTER(addr) (addr & ~3) +/* bits for 68040 MMU Transparent Translation Registers */ +#define M68K_TTR_ADDR_BASE 0xff000000 +#define M68K_TTR_ADDR_MASK 0x00ff0000 +#define M68K_TTR_ADDR_MASK_SHIFT 8 +#define M68K_TTR_ENABLED 0x00008000 +#define M68K_TTR_SFIELD 0x00006000 +#define M68K_TTR_SFIELD_USER 0x0000 +#define M68K_TTR_SFIELD_SUPER 0x2000 + /* m68k Control Registers */ /* ColdFire */ |