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| author | Cathy Zhang <cathy.zhang@intel.com> | 2020-04-13 14:52:38 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-06-10 12:10:27 -0400 |
| commit | 353f98c9ad52ff4b8cfe553c90be04f747a14c98 (patch) | |
| tree | 9bba0c487797641b43e752af185eb3925489d61b /target/i386/cpu.c | |
| parent | c781a2cc423155079acf45e5ce79e6635f109fc4 (diff) | |
| download | qemu-353f98c9ad52ff4b8cfe553c90be04f747a14c98.zip | |
x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
AVX512_VP2INTERSECT compute vector pair intersection to a pair
of mask registers, which is introduced with intel Tiger Lake,
defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].
Refer to the following release spec:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5705cda86..e89d9fa894 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -985,7 +985,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, - NULL, NULL, "md-clear", NULL, + "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* pconfig */, NULL, NULL, NULL, NULL, NULL, |