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authorSven Schnelle <svens@stackframe.org>2019-09-13 12:17:13 +0200
committerRichard Henderson <richard.henderson@linaro.org>2019-09-14 15:39:24 -0400
commit4845f01518fcc0b77f8b000651f9a5cc27d9f730 (patch)
tree97d06d9eb7f6da9212a17067a30979e9e55222db /target/hppa
parent85182c96de61f0b600bbe834d5a23e713162e892 (diff)
downloadqemu-4845f01518fcc0b77f8b000651f9a5cc27d9f730.zip
target/hppa: prevent trashing of temporary in trans_mtctl()
nullify_over() calls brcond which destroys all temporaries. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190913101714.29019-2-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa')
-rw-r--r--target/hppa/translate.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 53e17d8963..b12525d535 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2214,10 +2214,11 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
{
unsigned ctl = a->t;
- TCGv_reg reg = load_gpr(ctx, a->r);
+ TCGv_reg reg;
TCGv_reg tmp;
if (ctl == CR_SAR) {
+ reg = load_gpr(ctx, a->r);
tmp = tcg_temp_new();
tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1);
save_or_nullify(ctx, cpu_sar, tmp);
@@ -2232,6 +2233,8 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
+ reg = load_gpr(ctx, a->r);
+
switch (ctl) {
case CR_IT:
gen_helper_write_interval_timer(cpu_env, reg);