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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-10-27 18:33:23 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-01-30 10:22:26 -0800 |
| commit | 63300a00ab52c770f8a76218d4a3a75e0db8a6d0 (patch) | |
| tree | c1e3d56a2cecf0aec0d2d6d736c5b2cfc487788a /target/hppa/translate.c | |
| parent | 8d6ae7fb3a9c4369979bcc7188966fa725eed033 (diff) | |
| download | qemu-63300a00ab52c770f8a76218d4a3a75e0db8a6d0.zip | |
target/hppa: Implement P*TLB and P*TLBE insns
We now have all of the TLB manipulation instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/translate.c')
| -rw-r--r-- | target/hppa/translate.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c02d107041..5b77688fc0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2397,6 +2397,42 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } + +static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned m = extract32(insn, 5, 1); + unsigned sp; + unsigned rx = extract32(insn, 16, 5); + unsigned rb = extract32(insn, 21, 5); + unsigned is_data = insn & 0x1000; + unsigned is_local = insn & 0x40; + TCGv_tl addr; + TCGv_reg ofs; + + if (is_data) { + sp = extract32(insn, 14, 2); + } else { + sp = ~assemble_sr3(insn); + } + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, rb, rx, 0, 0, sp, m, false); + if (m) { + save_gpr(ctx, rb, ofs); + } + if (is_local) { + gen_helper_ptlbe(cpu_env); + } else { + gen_helper_ptlb(cpu_env, addr); + } + + /* Exit TB for TLB change if mmu is enabled. */ + return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + ? DISAS_IAQ_N_STALE : DISAS_NEXT); +} #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_mem_mgmt[] = { @@ -2420,6 +2456,10 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04000040u, 0xfc001fffu, trans_ixtlbx }, /* iitlba */ { 0x04001000u, 0xfc001fffu, trans_ixtlbx }, /* idtlbp */ { 0x04001040u, 0xfc001fffu, trans_ixtlbx }, /* idtlba */ + { 0x04000200u, 0xfc001fdfu, trans_pxtlbx }, /* pitlb */ + { 0x04000240u, 0xfc001fdfu, trans_pxtlbx }, /* pitlbe */ + { 0x04001200u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlb */ + { 0x04001240u, 0xfc001fdfu, trans_pxtlbx }, /* pdtlbe */ #endif }; |