diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-12 09:36:07 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-02-12 08:59:10 -0800 |
| commit | 8340f5341e7562c0328703f1baa9af88ead4d775 (patch) | |
| tree | 0a38a1a329296ebf904c4be7fb243b8ca5925aa9 /target/hppa/insns.decode | |
| parent | 30878590bc55066bb93efbe4f2bba9b02b0f06a9 (diff) | |
| download | qemu-8340f5341e7562c0328703f1baa9af88ead4d775.zip | |
target/hppa: Convert direct and indirect branches
Tested-by: Helge Deller <deller@gmx.de>
Tested-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/insns.decode')
| -rw-r--r-- | target/hppa/insns.decode | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 987cb8738b..4897dbd4dd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -24,7 +24,9 @@ %assemble_sr3 13:1 14:2 %assemble_sr3x 13:1 14:2 !function=expand_sr3x -%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 +%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 +%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 +%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 %sm_imm 16:10 !function=expand_sm_imm @@ -210,3 +212,33 @@ depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16 depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16 + +#### +# Branch External +#### + +&BE b l n disp sp +@be ...... b:5 ..... ... ........... n:1 . \ + &BE disp=%assemble_17 sp=%assemble_sr3 + +be 111000 ..... ..... ... ........... . . @be l=0 +be 111001 ..... ..... ... ........... . . @be l=31 + +#### +# Branch +#### + +&BL l n disp +@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 + +# B,L and B,L,PUSH +bl 111010 ..... ..... 000 ........... . . @bl +bl 111010 ..... ..... 100 ........... . . @bl +# B,L (long displacement) +bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ + disp=%assemble_22 +b_gate 111010 ..... ..... 001 ........... . . @bl +blr 111010 l:5 x:5 010 00000000000 n:1 0 +bv 111010 b:5 x:5 110 00000000000 n:1 0 +bve 111010 b:5 00000 110 10000000000 n:1 - l=0 +bve 111010 b:5 00000 111 10000000000 n:1 - l=2 |