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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-01-06 16:02:27 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-01-31 05:30:50 -0800 |
| commit | 7b93dab51e929d7c2878cb5ad92b4419e3318e73 (patch) | |
| tree | 82e1181a5bae861b3584ec076488284093d30c84 /target/hppa/cpu.h | |
| parent | 95412a612867ea200b8f5285a4de3c059b873a55 (diff) | |
| download | qemu-7b93dab51e929d7c2878cb5ad92b4419e3318e73.zip | |
target/hppa: Enable MTTCG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/cpu.h')
| -rw-r--r-- | target/hppa/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 70af823a15..7640c81221 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" |